On 01/03/2016 19:28, Richard Henderson wrote:
> In non-64-bit modes, the instruction always stores 16 bits.
> But in 64-bit mode, when the destination is a register, the
> instruction can write 32 or 64 bits.
>
> Signed-off-by: Richard Henderson <r...@twiddle.net>
> ---
> target-i386/translate.c | 14 ++++++++------
> 1 file changed, 8 insertions(+), 6 deletions(-)
>
> diff --git a/target-i386/translate.c b/target-i386/translate.c
> index 1413069..482e93a 100644
> --- a/target-i386/translate.c
> +++ b/target-i386/translate.c
> @@ -7282,12 +7282,14 @@ static target_ulong disas_insn(CPUX86State *env,
> DisasContext *s,
>
> CASE_MODRM_OP(4): /* smsw */
> gen_svm_check_intercept(s, pc_start, SVM_EXIT_READ_CR0);
> -#if defined TARGET_X86_64 && defined HOST_WORDS_BIGENDIAN
> - tcg_gen_ld32u_tl(cpu_T0, cpu_env, offsetof(CPUX86State, cr[0]) +
> 4);
> -#else
> - tcg_gen_ld32u_tl(cpu_T0, cpu_env, offsetof(CPUX86State, cr[0]));
> -#endif
> - gen_ldst_modrm(env, s, modrm, MO_16, OR_TMP0, 1);
> + tcg_gen_ld_tl(cpu_T0, cpu_env, offsetof(CPUX86State, cr[0]));
> + if (CODE64(s)) {
> + mod = (modrm >> 6) & 3;
> + ot = (mod != 3 ? MO_16 : s->dflag);
> + } else {
> + ot = MO_16;
> + }
> + gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 1);
> break;
>
> CASE_MODRM_OP(6): /* lmsw */
>
Thanks, queued together with the modrm=3 fix.
Paolo
