Hi Andrew,
I thought the timer that was not implemented was the local timer
(located at 0x40000034) and that the core timers interrupt control
registers starting at 0x40000040 were the per-core timers.
Can you please point me to the documentation about this ARM per-core timers?
Thanks,
Antonio Huete
Andrew Baumann <andrew.baum...@microsoft.com> escribió:
Hi Antonio,
From: Antonio Huete Jiménez [mailto:tuxi...@quantumachine.net]
Sent: Wednesday, 16 March 2016 3:40 PM
Hi,
I am experiencing what I think it's an issue with -M raspi2 and
interrupts in a baremetal application.
According to this document
(https://www.raspberrypi.org/documentation/hardware/raspberrypi/bcm2
836/QA7_rev3.4.pdf), and if I understood it correctly, you can enable timer
interrupts for core0 by setting bit 0 at 0x40000040 and you can trigger them
by using the ARM Generic
Timer.
With this procedure I can reliably trigger that timer interrupt in the
real hardware by setting CNTP_CTL and CNTP_TVAL but on qemu it doesn't
seem to be triggered.
Can somebody please tell me what I might be doing wrong?
I don't think you're doing anything wrong; we just don't model this
timer hardware yet (neither Linux nor Windows needs it). If you want
to take a stab at adding it, the relevant hardware emulation is
hw/intc/bcm2836_control.c.
If you're willing to use different timer sources, then I suggest
looking at the ARM per-core timers. I also have Gregory's emulation
code for the other bcm2835 timers in my private github, and I hope
to submit to upstream qemu after the current freeze, since it is
needed for pi1 Linux support.
Cheers,
Andrew
