On 31/03/16 17:49, Peter Maydell wrote: > The TCR_EL2 regdef was incorrectly using the vmsa_tcr_el1_write > function for writes. Since TCR_EL2 doesn't have the A1 bit that > TCR_EL1 does, we don't need to do a tlb_flush() when it is written. > Remove the unnecessary .writefn and also the harmless but unneeded > .raw_writefn and .resetfn definitions.
How about TCR_EL3 which doesn't have A1 bit as well? Kind regards, Sergey > > Signed-off-by: Peter Maydell <peter.mayd...@linaro.org> > --- > target-arm/helper.c | 6 ++++-- > 1 file changed, 4 insertions(+), 2 deletions(-) > > diff --git a/target-arm/helper.c b/target-arm/helper.c > index 09638b2..4dbd844 100644 > --- a/target-arm/helper.c > +++ b/target-arm/helper.c > @@ -3559,8 +3559,10 @@ static const ARMCPRegInfo el2_cp_reginfo[] = { > .resetvalue = 0 }, > { .name = "TCR_EL2", .state = ARM_CP_STATE_BOTH, > .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 2, > - .access = PL2_RW, .writefn = vmsa_tcr_el1_write, > - .resetfn = vmsa_ttbcr_reset, .raw_writefn = raw_write, > + .access = PL2_RW, > + /* no .writefn needed as this can't cause an ASID change; > + * no .raw_writefn or .resetfn needed as we never use mask/base_mask > + */ > .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[2]) }, > { .name = "VTCR", .state = ARM_CP_STATE_AA32, > .cp = 15, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2,