On Wed, Apr 13, 2016 at 07:44:54AM -0700, Jan Kiszka wrote: [...] > > One thing I am curious about: I see that in vtd spec 5.1.5.1: > > > > "RTE bits 10:8 is programmed to 000b (Fixed) to force the SHV > > (SubHandle Valid) field as Clear in the interrupt address > > generated." > > > > So... In real IOMMU hardwares, IOAPIC interrupt will finally be > > translated to MSI as well? am I understanding it correctly? > > It will be translated into something that the IR unit can receive - > whatever that is technically. Logically, there is no difference to MSIs > received from PCI devices.
Ok. I see there are still differences between IOAPIC and MSI, e.g., for IOAPIC entries, it has "Interrupt Input Pin Polarity", which is bit 13 of the entry, to show whether 1 or 0 is taken as assertion for level-triggered interrupts. While in MSI, I assume assertion will be 1 always. Can I take it as "obsolete" and we will never use it? If to take IOAPIC entries as MSI messages, all these extra bits will be dropped (it's dropped in ioapic_service() already, but not sure whether we will pick them up in the future). > > > > > Btw, if to use the way you suggested, the patch content would > > possibly be very alike the one you and Rita has posted, which is: > > > > https://lists.gnu.org/archive/html/qemu-devel/2016-03/msg01933.html > > > > I will only pick up those lines I needed in supporting IOAPIC. If > > so, do you mind I add your s-o-b as well above mine (maybe add > > Rita's too)? > > If a patch is almost identical, add your [Peter: my changes...] line and > your signed of to it. If it is more modified, claim authorship and just > refer to the original authors in the commit log. Ok. Thanks. -- peterx