Hi Alex, I finally solved the issue I had, the branch is working well as far as I can say. The work I will share, in addition to making the LL/SC work mttcg-aware, extends the various TLB flushes calls with the query-based mechanism: the requesting CPU queries the flushes to the target CPUs and wait them for completion.
Sorry for the delay, I have been quite busy. I just need to polish some commits, than (this week) I will share the branch. Best regards, alvise On Mon, May 23, 2016 at 12:57 PM, Alex Bennée <alex.ben...@linaro.org> wrote: > Hi, > > It's been a while since the last sync-up call. Have we got any topics to > discuss today? > > Sergey and I (with a little Paolo) have spent some of last week delving > into the locking hierarchy w.r.t to tb_lock vs mmap_lock to see if there > is any simplification to be had. I'm not sure if this is a topic > conducive to a phone call instead of the mailing list but if others want > to discuss it we can add it as an agenda item. > > We also have a new member of the team. Pranith has joined as a GSoC > student. He'll be looking at memory ordering with his first pass at the > problem looking to solve the store-after-load issues which do show up on > ARM-on-x86 (see my testcase). > > Alvise, is there any help you need with the LL/SC stuff? The MTTCG aware > version has been taking some time so would it be worth sharing the > issues you have hit with the group? > > Emilio, is there anything you want to add? I've been following the QHT > stuff which is a really positive addition which my v3 base patches is > based upon (making the hot-path non lock contended). Do you have > anything in the works above that? > > Cheers, > > -- > Alex Bennée >
