On 05/30/2016 12:59 AM, peer.ad...@c-lab.de wrote:
> From: Peer Adelt <peer.ad...@c-lab.de>
>
> If D[15] is != sign_ext(const4) then PC will be set to (PC +
> zero_ext(disp4 + 16)).
>
> Signed-off-by: Peer Adelt <peer.ad...@c-lab.de>
> ---
> target-tricore/translate.c | 1 +
> target-tricore/tricore-opcodes.h | 1 +
> 2 files changed, 2 insertions(+)
>
> diff --git a/target-tricore/translate.c b/target-tricore/translate.c
> index 2145f64..9ad9fcc 100644
> --- a/target-tricore/translate.c
> +++ b/target-tricore/translate.c
> @@ -3363,6 +3363,7 @@ static void gen_compute_branch(DisasContext *ctx,
> uint32_t opc, int r1,
> gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[15], constant, offset);
> break;
> case OPC1_16_SBC_JNE:
> + case OPC1_16_SBC_JNE16:
> gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[15], constant, offset);
> break;
You forgot to call gen_compute_branch() from decode_16Bit_opc() for this
instruction, which should do the addition of 16 to disp4. Also please
add a check for 1.6+ ISA as suggested for the patch before.
Cheers,
Bastian
