From: Peer Adelt <peer.ad...@c-lab.de>
If D[15] is != sign_ext(const4) then PC will be set to (PC +
zero_ext(disp4 + 16)).
Signed-off-by: Peer Adelt <peer.ad...@c-lab.de>
---
target-tricore/translate.c | 11 +++++++++++
target-tricore/tricore-opcodes.h | 1 +
2 files changed, 12 insertions(+)
diff --git a/target-tricore/translate.c b/target-tricore/translate.c
index 960ee33..21732f8 100644
--- a/target-tricore/translate.c
+++ b/target-tricore/translate.c
@@ -3363,6 +3363,7 @@ static void gen_compute_branch(DisasContext *ctx,
uint32_t opc, int r1,
gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[15], constant, offset);
break;
case OPC1_16_SBC_JNE:
+ case OPC1_16_SBC_JNE16:
gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[15], constant, offset);
break;
/* SBRN-format jumps */
@@ -4097,6 +4098,16 @@ static void decode_16Bit_opc(CPUTriCoreState *env,
DisasContext *ctx)
const16 = MASK_OP_SBC_CONST4_SEXT(ctx->opcode);
gen_compute_branch(ctx, op1, 0, 0, const16, address);
break;
+ case OPC1_16_SBC_JEQ16:
+ case OPC1_16_SBC_JNE16:
+ if (tricore_feature(env, TRICORE_FEATURE_16)) {
+ address = MASK_OP_SBC_DISP4(ctx->opcode);
+ const16 = MASK_OP_SBC_CONST4_SEXT(ctx->opcode);
+ gen_compute_branch(ctx, op1, 0, 0, const16, address + 16);
+ } else {
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
+ }
+ break;
/* SBRN-format */
case OPC1_16_SBRN_JNZ_T:
case OPC1_16_SBRN_JZ_T:
diff --git a/target-tricore/tricore-opcodes.h b/target-tricore/tricore-opcodes.h
index 2f25613..7925354 100644
--- a/target-tricore/tricore-opcodes.h
+++ b/target-tricore/tricore-opcodes.h
@@ -318,6 +318,7 @@ enum {
OPC1_16_SBR_JLEZ = 0x8e,
OPC1_16_SBR_JLTZ = 0x0e,
OPC1_16_SBC_JNE = 0x5e,
+ OPC1_16_SBC_JNE16 = 0xde,
OPC1_16_SBR_JNE = 0x7e,
OPC1_16_SB_JNZ = 0xee,
OPC1_16_SBR_JNZ = 0xf6,
--
2.7.4
