Remove some incorrect code from arm_cpu_do_interrupt_aarch64()
which attempts to set the IL bit in the syndrome register based
on the value of env->thumb. This is wrong in several ways:
* IL doesn't indicate Thumb-vs-ARM, it indicates instruction
length (which may be 16 or 32 for Thumb and is always 32 for ARM)
* not every syndrome format uses IL like this -- for some IL is
always set, and for some it is always clear
* the code is changing esr_el[new_el] even for interrupt entry,
which is not supposed to modify ESR_ELx at all
Delete the code, and instead rely on the syndrome value in
env->exception.syndrome having already been set up with the
correct value of IL.
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Reviewed-by: Edgar E. Iglesias <edgar.igles...@xilinx.com>
Tested-by: Edgar E. Iglesias <edgar.igles...@xilinx.com>
Message-id: 1463487258-27468-3-git-send-email-peter.mayd...@linaro.org
---
target-arm/helper.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 9a6ff2e..86a094d 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -6365,9 +6365,6 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs)
env->elr_el[new_el] = env->pc;
} else {
env->banked_spsr[aarch64_banked_spsr_index(new_el)] = cpsr_read(env);
- if (!env->thumb) {
- env->cp15.esr_el[new_el] |= 1 << 25;
- }
env->elr_el[new_el] = env->regs[15];
aarch64_sync_32_to_64(env);
--
1.9.1
