Mark Rutland <mark.rutl...@arm.com> writes:
> On Mon, Jun 06, 2016 at 05:22:49PM +0100, Alex Bennée wrote:
>> Andrew Jones <drjo...@redhat.com> writes:
>> > +#define MPIDR_LEVEL_SHIFT(level) \
>> > + (((1 << level) >> 1) << 3)
>> > +#define MPIDR_AFFINITY_LEVEL(mpidr, level) \
>> > + ((mpidr >> MPIDR_LEVEL_SHIFT(level)) & 0xff)
>>
>> Doesn't Aff3 break this little macro? It sits at 32:39 with a gap for
>> MT, RES0, U, RES1 for bits 25:31
>
> It works, it's just a little bit magic:
Ahh the magic was too subtle for my eyes, perhaps a comment for the
wary.
>
> (gdb) p (((1 << 0) >> 1) << 3)
> $1 = 0
> (gdb) p (((1 << 1) >> 1) << 3)
> $2 = 8
> (gdb) p (((1 << 2) >> 1) << 3)
> $3 = 16
> (gdb) p (((1 << 3) >> 1) << 3)
> $4 = 32
> (gdb)
>
> We do the same in arch/arm64/include/asm/cputype.h since b058450f38c337d1
> ("arm64: kernel: add MPIDR_EL1 accessors macros").
I see the truth of it ;-)
>
> Thanks,
> Mark.
--
Alex Bennée
