ICH9 LPC bridge is used to route PCI IRQs to GSI. The root PCI bus reference is
required to setup the routing. According to specification, the bridge is
connected to root bus. Hence, there is no reason to setup the routing
externally.
The patch moves the setup code to 'realize' method. Also several related
functions are made static because they are no needed outside the bridge
implementation any more.
Signed-off-by: Efimov Vasily <r...@ispras.ru>
---
hw/i386/pc_q35.c | 3 ---
hw/isa/lpc_ich9.c | 10 +++++++---
include/hw/i386/ich9.h | 3 ---
3 files changed, 7 insertions(+), 9 deletions(-)
diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c
index 4661be2..11ca751 100644
--- a/hw/i386/pc_q35.c
+++ b/hw/i386/pc_q35.c
@@ -195,9 +195,6 @@ static void pc_q35_init(MachineState *machine)
for (i = 0; i < ISA_NUM_IRQS; i++) {
qdev_connect_gpio_out(lpc_dev, i, gsi[i]);
}
- pci_bus_irqs(host_bus, ich9_lpc_set_irq, ich9_lpc_map_irq, ich9_lpc,
- ICH9_LPC_NB_PIRQS);
- pci_bus_set_route_irq_fn(host_bus, ich9_route_intx_pin_to_irq);
isa_bus = ich9_lpc->isa_bus;
if (kvm_pic_in_kernel()) {
diff --git a/hw/isa/lpc_ich9.c b/hw/isa/lpc_ich9.c
index 798d9e7..e9929af 100644
--- a/hw/isa/lpc_ich9.c
+++ b/hw/isa/lpc_ich9.c
@@ -266,7 +266,7 @@ static void ich9_lpc_update_apic(ICH9LPCState *lpc, int gsi)
qemu_set_irq(lpc->ioapic[gsi], level);
}
-void ich9_lpc_set_irq(void *opaque, int pirq, int level)
+static void ich9_lpc_set_irq(void *opaque, int pirq, int level)
{
ICH9LPCState *lpc = opaque;
@@ -280,7 +280,7 @@ void ich9_lpc_set_irq(void *opaque, int pirq, int level)
/* return the pirq number (PIRQ[A-H]:0-7) corresponding to
* a given device irq pin.
*/
-int ich9_lpc_map_irq(PCIDevice *pci_dev, int intx)
+static int ich9_lpc_map_irq(PCIDevice *pci_dev, int intx)
{
BusState *bus = qdev_get_parent_bus(&pci_dev->qdev);
PCIBus *pci_bus = PCI_BUS(bus);
@@ -291,7 +291,7 @@ int ich9_lpc_map_irq(PCIDevice *pci_dev, int intx)
return lpc->irr[PCI_SLOT(pci_dev->devfn)][intx];
}
-PCIINTxRoute ich9_route_intx_pin_to_irq(void *opaque, int pirq_pin)
+static PCIINTxRoute ich9_route_intx_pin_to_irq(void *opaque, int pirq_pin)
{
ICH9LPCState *lpc = opaque;
PCIINTxRoute route;
@@ -641,6 +641,10 @@ static void ich9_lpc_realize(PCIDevice *d, Error **errp)
qdev_init_gpio_out(dev, lpc->ioapic, IOAPIC_NUM_PINS);
isa_bus_irqs(isa_bus, lpc->pic);
+
+ pci_bus_irqs(lpc->d.bus, ich9_lpc_set_irq, ich9_lpc_map_irq, lpc,
+ ICH9_LPC_NB_PIRQS);
+ pci_bus_set_route_irq_fn(lpc->d.bus, ich9_route_intx_pin_to_irq);
}
static bool ich9_rst_cnt_needed(void *opaque)
diff --git a/include/hw/i386/ich9.h b/include/hw/i386/ich9.h
index e800e68..3fca7ea 100644
--- a/include/hw/i386/ich9.h
+++ b/include/hw/i386/ich9.h
@@ -14,9 +14,6 @@
#include "hw/acpi/ich9.h"
#include "hw/pci/pci_bus.h"
-void ich9_lpc_set_irq(void *opaque, int irq_num, int level);
-int ich9_lpc_map_irq(PCIDevice *pci_dev, int intx);
-PCIINTxRoute ich9_route_intx_pin_to_irq(void *opaque, int pirq_pin);
void ich9_lpc_pm_init(PCIDevice *pci_lpc, bool smm_enabled);
I2CBus *ich9_smb_init(PCIBus *bus, int devfn, uint32_t smb_io_base);
--
2.7.4
