On Tue, 21 Jun 2016 16:50:17 +1000 David Gibson <da...@gibson.dropbear.id.au> wrote:
> On Tue, Jun 21, 2016 at 11:14:03AM +1000, Alexey Kardashevskiy wrote: > > There are going to be multiple IOMMUs per a container. This moves > > the single host IOMMU parameter set to a list of VFIOHostDMAWindow. > > > > This should cause no behavioral change and will be used later by > > the SPAPR TCE IOMMU v2 which will also add a vfio_host_win_del() helper. > > > > Signed-off-by: Alexey Kardashevskiy <a...@ozlabs.ru> > > Reviewed-by: David Gibson <da...@gibson.dropbear.id.au> > > Looks ok to me. Again, Alex, your tree or mine? I gave the previous patch a nak, it needs a respin, but this one looks ok. I don't currently have anything pending that would conflict with this, afaik, so it's ok with me if you want to pull it through your tree. I'll ack the respin. > One minor point.. > [snip] > > @@ -878,17 +908,14 @@ static int vfio_connect_container(VFIOGroup *group, > > AddressSpace *as) > > * existing Type1 IOMMUs generally support any IOVA we're > > * going to actually try in practice. > > */ > > - container->min_iova = 0; > > - container->max_iova = (hwaddr)-1; > > - > > - /* Assume just 4K IOVA page size */ > > - container->iova_pgsizes = 0x1000; > > info.argsz = sizeof(info); > > ret = ioctl(fd, VFIO_IOMMU_GET_INFO, &info); > > /* Ignore errors */ > > - if ((ret == 0) && (info.flags & VFIO_IOMMU_INFO_PGSIZES)) { > > - container->iova_pgsizes = info.iova_pgsizes; > > + if (ret || !(info.flags & VFIO_IOMMU_INFO_PGSIZES)) { > > + /* Assume 4k IOVA page size */ > > + info.iova_pgsizes = 4096; > > } > > + vfio_host_win_add(container, 0, (hwaddr)-1, info.iova_pgsizes); > > I don't think it needs to hold this patch up, but at some point we > should work out the real range covered by the x86 IOMMU tables and put > that in here. I'm pretty sure it won't actually be 2^64-1. Between this patch, some work that Eric is doing that would allow us to exclude the MSI range, and the capability chains that we can add to the IOMMU_GET_INFO ioctl to describe both the extent and the reserved MSI area, I think we're getting close to being able to do that. On AMD I think we do have a full 64bit address space, but VT-d is definitely not. Thanks, Alex