Am 03.08.2016 um 00:05 schrieb John Snow:
> ATA8-APT defines the state transitions for both a host controller and
> for the hardware device during the lifecycle of a DMA transfer, in
> section 9.7 "DMA command protocol."
>
> One of the interesting tidbits here is that when a device transitions
> from DDMA0 ("Prepare state") to DDMA1 ("Data_Transfer State"), it can
> choose to set either BSY or DRQ to signal this transition, but not both.
>
> as ide_sector_dma_start is the last point in our preparation process
> before we begin the real data transfer process (for either AHCI or BMDMA),
> this is the correct transition point for DDMA0 to DDMA1.
>
> I have chosen !BSY && DRQ for QEMU to make the transition from DDMA0 the
> most obvious.
>
> Reported-by: Benjamin David Lunt <f...@fysnet.net>
> Signed-off-by: John Snow <js...@redhat.com>
> ---
> hw/ide/core.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/hw/ide/core.c b/hw/ide/core.c
> index d117b7c..e961d42 100644
> --- a/hw/ide/core.c
> +++ b/hw/ide/core.c
> @@ -907,7 +907,7 @@ eot:
>
> static void ide_sector_start_dma(IDEState *s, enum ide_dma_cmd dma_cmd)
> {
> - s->status = READY_STAT | SEEK_STAT | DRQ_STAT | BUSY_STAT;
> + s->status = READY_STAT | SEEK_STAT | DRQ_STAT;
> s->io_buffer_size = 0;
> s->dma_cmd = dma_cmd;This patch fixes the reported test case, thank you. Tested-by: Stefan Weil <s...@weilnetz.de>
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