On 09/08/2016 03:01 AM, Leon Alrae wrote: > Make use of memory barrier TCG opcode in MIPS front end. > > Signed-off-by: Leon Alrae <leon.al...@imgtec.com> > --- > v2: > * generate weaker barriers according to stype > --- > target-mips/translate.c | 32 ++++++++++++++++++++++++++++++-- > 1 file changed, 30 insertions(+), 2 deletions(-)
Ah, even better. Reviewed-by: Richard Henderson <r...@twiddle.net> > +static void gen_sync(int stype) > +{ > + TCGOrder tcg_mo = TCG_BAR_SC; > + > + switch (stype) { > + case 0x4: /* SYNC_WMB */ > + tcg_mo |= TCG_MO_ST_ST; > + break; > + case 0x10: /* SYNC_MB */ > + tcg_mo |= TCG_MO_ALL; > + break; > + case 0x11: /* SYNC_ACQUIRE */ > + tcg_mo |= TCG_MO_LD_LD | TCG_MO_LD_ST; > + break; > + case 0x12: /* SYNC_RELEASE */ > + tcg_mo |= TCG_MO_ST_ST | TCG_MO_LD_ST; > + break; > + case 0x13: /* SYNC_RMB */ > + tcg_mo |= TCG_MO_LD_LD; > + break; > + default: > + tcg_mo |= TCG_MO_ALL; > + break; > + } See git://github.com/rth7680/qemu.git tcg-next wherein this suggests that some enhancement is desired in tcg/mips/ as well. Not that I have a mips32r6 board with which to test. Would you or James Hogan be able to improve that? r~