On Fri, 23 Sep 2016, Richard Henderson wrote: > While increasing the max per insn is indeed one way to approach this, aarch64 > is being remarkably inefficient in this case. With the following, I see a > reduction from 387 ops to 261 ops; for a 64-bit host, the reduction is from > 258 ops to 195 ops.
261 ops plus ops generated in gen_intermediate_code_a64 after the loop plus ops from optimization may still require an increase from 266, of course (I don't know how to bound the number of ops space must still be available for after translating an instruction has resulted in tcg_op_buf_full() being true, but my testing had cases where it was at least 8). -- Joseph S. Myers jos...@codesourcery.com
