Re: [Qemu-devel] [PATCH 07/18] target-riscv: Add Loads/Stores, FP Loads/Stores

[Richard Henderson]

On 09/26/2016 03:56 AM, Sagar Karandikar wrote:

Signed-off-by: Sagar Karandikar <sag...@eecs.berkeley.edu>
---
 target-riscv/translate.c | 117 +++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 117 insertions(+)

diff --git a/target-riscv/translate.c b/target-riscv/translate.c
index d8044cf..767cdbe 100644
--- a/target-riscv/translate.c
+++ b/target-riscv/translate.c
@@ -72,6 +72,10 @@ static const char * const fpr_regnames[] = {
   "fs8", "fs9", "fs10", "fs11", "ft8", "ft9", "ft10", "ft11"
 };

+/* convert riscv funct3 to qemu memop for load/store */
+static int tcg_memop_lookup[] = { MO_SB, MO_TESW, MO_TESL, MO_TEQ, MO_UB,
+    MO_TEUW, MO_TEUL };

Const, and formatting

static const TCGMemOp tcg_memop_lookup[] = {
    ....
};

although...

+static inline void gen_load(DisasContext *ctx, uint32_t opc, int rd, int rs1,
+        int16_t imm)
+{
+    target_long uimm = (target_long)imm; /* sign ext 16->64 bits */
+    TCGv t0 = tcg_temp_new();
+    TCGv t1 = tcg_temp_new();
+    gen_get_gpr(t0, rs1);
+    tcg_gen_addi_tl(t0, t0, uimm); /* */
+    int memop = (opc >> 12) & 0x7;
+
+#if defined(TARGET_RISCV64)
+    if (memop == 0x7) {
+#else
+    if (memop == 0x7 || memop == 0x3 || memop == 0x6) {
+#endif
+        kill_unknown(ctx, RISCV_EXCP_ILLEGAL_INST);
+    } else {
+        tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, tcg_memop_lookup[memop]);

... considering the set of if's, maybe better as

static const int tcg_memop_lookup[8] = {
    [0 ... 7] = -1,
    [0] = MO_SB,
    [1] = MO_TESW,
    [2] = MO_TESL,
    [4] = MO_UB,
    [5] = MO_TEUW,
#ifdef TARGET_RISCV64
    [3] = MO_TEQ,
    [6] = MO_TEUL,
#endif
};

and then have

    memop = tcg_memop_lookup[memop];
    if (memop < 0) {
        kill_unknown(ctx, RISCV_EXCP_ILLEGAL_INST);
    } else {
        tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, memop);
    }


r~