On Tue, Jan 10, 2017 at 06:44:08PM +0000, Peter Maydell wrote: > To run a VM in 32-bit EL1 our AArch32 interrupt handling code > needs to be able to cope with VIRQ and VFIQ exceptions. > These behave like IRQ and FIQ except that we don't need to try > to route them to Monitor mode. > > Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
We could possibly avoid some duplication with EXCP_IRQ and _FIQ but either way works: Reviewed-by: Edgar E. Iglesias <edgar.igles...@xilinx.com> > --- > target/arm/helper.c | 14 ++++++++++++++ > 1 file changed, 14 insertions(+) > > diff --git a/target/arm/helper.c b/target/arm/helper.c > index 8dcabbf..dc90986 100644 > --- a/target/arm/helper.c > +++ b/target/arm/helper.c > @@ -6403,6 +6403,20 @@ static void arm_cpu_do_interrupt_aarch32(CPUState *cs) > } > offset = 4; > break; > + case EXCP_VIRQ: > + new_mode = ARM_CPU_MODE_IRQ; > + addr = 0x18; > + /* Disable IRQ and imprecise data aborts. */ > + mask = CPSR_A | CPSR_I; > + offset = 4; > + break; > + case EXCP_VFIQ: > + new_mode = ARM_CPU_MODE_FIQ; > + addr = 0x1c; > + /* Disable FIQ, IRQ and imprecise data aborts. */ > + mask = CPSR_A | CPSR_I | CPSR_F; > + offset = 4; > + break; > case EXCP_SMC: > new_mode = ARM_CPU_MODE_MON; > addr = 0x08; > -- > 2.7.4 >