On 01/17/2017 06:34 PM, mar.krzeminski wrote:
>>>> +static void test_write_page_mem(void)
>>>> +{
>>>> + uint32_t my_page_addr = 0x15000 * PAGE_SIZE;
>>>> + uint32_t page[PAGE_SIZE / 4];
>>>> + int i;
>>>> +
>>>> + /* Enable 4BYTE mode for controller. This is should be strapped by
>>>> + * HW for CE0 anyhow.
>>>> + */
>>>> + spi_ce_ctrl(1 << CRTL_EXTENDED0);
>>>> +
>>>> + /* Enable 4BYTE mode for flash. */
>>>> + spi_conf(CONF_ENABLE_W0);
>>>> + spi_ctrl_start_user();
>>>> + writeb(ASPEED_FLASH_BASE, EN_4BYTE_ADDR);
>>>> + writeb(ASPEED_FLASH_BASE, WREN);
>>> This is a bit tricky, in real HW you need to set WREN
>>> before issue PROGRAM command on most of the devices.
>>> If there is no cache in emulated in SMC controller
>>> (if any in HW), WREN should be issued before every write.
>> ah yes. So to be more precise, WREN should be moved in the
>> loop below.
> Yes.
So, as the test is writing one page only, I think the code is
currently correct.
I will come up with your suggested cleanups and more tests
later on, may be in the 2.9 time frame.
Thanks for the review,
C.
