On Wed, Sep 15, 2010 at 02:38:17PM +0900, Isaku Yamahata wrote:
> add pcie constants to pcie_regs.h.
> Those constants should go to Linux pci_regs.h and then the file should
> go away eventually.
>
> Signed-off-by: Isaku Yamahata <yamah...@valinux.co.jp>
> ---
> Changes v2 -> v3:
> - moved out pcie constants from pcie.c to pcie_regs.h.
> - removed unused macros
> ---
> hw/pcie_regs.h | 170
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> 1 files changed, 170 insertions(+), 0 deletions(-)
> create mode 100644 hw/pcie_regs.h
>
> diff --git a/hw/pcie_regs.h b/hw/pcie_regs.h
> new file mode 100644
> index 0000000..abd39ef
> --- /dev/null
> +++ b/hw/pcie_regs.h
> @@ -0,0 +1,170 @@
> +/*
> + * pcie.c
> + *
> + * Copyright (c) 2010 Isaku Yamahata <yamahata at valinux co jp>
> + * VA Linux Systems Japan K.K.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License along
> + * with this program; if not, see <http://www.gnu.org/licenses/>.
I don't think we want these comments in this header.
The constants are from spec, we don't want to copyright them.
Copyright protecting headers seems generally not useful, and these notices do
take up the most valuable space in header: at the beginning.
> + */
> +#ifndef QEMU_PCIE_REGS_H
> +#define QEMU_PCIE_REGS_H
> +
> +/*
> + * TODO:
> + * Those constants and macros should be go to Linux pci_regs.h
> + * Once they're merged, they will go away.
> + */
> +
> +/* express capability */
> +
> +#define PCI_EXP_VER2_SIZEOF 0x3c /* express capability of ver. 2
> */
> +#define PCI_EXT_CAP_VER_SHIFT 16
> +#define PCI_EXT_CAP_NEXT_SHIFT 20
> +#define PCI_EXT_CAP_NEXT_MASK (0xffc << PCI_EXT_CAP_NEXT_SHIFT)
> +
> +#define PCI_EXT_CAP(id, ver, next) \
> + ((id) | \
> + ((ver) << PCI_EXT_CAP_VER_SHIFT) | \
> + ((next) << PCI_EXT_CAP_NEXT_SHIFT))
> +
> +#define PCI_EXT_CAP_ALIGN 4
> +#define PCI_EXT_CAP_ALIGNUP(x) \
> + (((x) + PCI_EXT_CAP_ALIGN - 1) & ~(PCI_EXT_CAP_ALIGN - 1))
> +
> +/* PCI_EXP_FLAGS */
> +#define PCI_EXP_FLAGS_VER2 2 /* for now, supports only ver. 2 */
> +#define PCI_EXP_FLAGS_IRQ_SHIFT (ffs(PCI_EXP_FLAGS_IRQ) - 1)
> +#define PCI_EXP_FLAGS_TYPE_SHIFT (ffs(PCI_EXP_FLAGS_TYPE) - 1)
> +
> +
> +/* PCI_EXP_LINK{CAP, STA} */
> +/* link speed */
> +#define PCI_EXP_LNK_LS_25 1
> +
> +#define PCI_EXP_LNK_MLW_SHIFT (ffs(PCI_EXP_LNKCAP_MLW) - 1)
> +#define PCI_EXP_LNK_MLW_1 (1 << PCI_EXP_LNK_MLW_SHIFT)
> +
> +/* PCI_EXP_LINKCAP */
> +#define PCI_EXP_LNKCAP_ASPMS_SHIFT (ffs(PCI_EXP_LNKCAP_ASPMS) - 1)
> +#define PCI_EXP_LNKCAP_ASPMS_0S (1 << PCI_EXP_LNKCAP_ASPMS_SHIFT)
> +
> +#define PCI_EXP_LNKCAP_PN_SHIFT (ffs(PCI_EXP_LNKCAP_PN) - 1)
> +
> +#define PCI_EXP_SLTCAP_PSN_SHIFT (ffs(PCI_EXP_SLTCAP_PSN) - 1)
> +
> +#define PCI_EXP_SLTCTL_IND_RESERVED 0x0
> +#define PCI_EXP_SLTCTL_IND_ON 0x1
> +#define PCI_EXP_SLTCTL_IND_BLINK 0x2
> +#define PCI_EXP_SLTCTL_IND_OFF 0x3
> +#define PCI_EXP_SLTCTL_AIC_SHIFT (ffs(PCI_EXP_SLTCTL_AIC) - 1)
> +#define PCI_EXP_SLTCTL_AIC_OFF \
> + (PCI_EXP_SLTCTL_IND_OFF << PCI_EXP_SLTCTL_AIC_SHIFT)
> +
> +#define PCI_EXP_SLTCTL_PIC_SHIFT (ffs(PCI_EXP_SLTCTL_PIC) - 1)
> +#define PCI_EXP_SLTCTL_PIC_OFF \
> + (PCI_EXP_SLTCTL_IND_OFF << PCI_EXP_SLTCTL_PIC_SHIFT)
> +
> +#define PCI_EXP_SLTCTL_SUPPORTED \
> + (PCI_EXP_SLTCTL_ABPE | \
> + PCI_EXP_SLTCTL_PDCE | \
> + PCI_EXP_SLTCTL_CCIE | \
> + PCI_EXP_SLTCTL_HPIE | \
> + PCI_EXP_SLTCTL_AIC | \
> + PCI_EXP_SLTCTL_PCC | \
> + PCI_EXP_SLTCTL_EIC)
> +
> +#define PCI_EXP_DEVCAP2_EFF 0x100000
> +#define PCI_EXP_DEVCAP2_EETLPP 0x200000
> +
> +#define PCI_EXP_DEVCTL2_EETLPPB 0x80
> +
> +/* ARI */
> +#define PCI_ARI_VER 1
> +#define PCI_ARI_SIZEOF 8
> +
> +/* AER */
> +#define PCI_ERR_VER 2
> +#define PCI_ERR_SIZEOF 0x48
> +
> +#define PCI_ERR_UNC_SDN 0x00000020 /* surprise down */
> +#define PCI_ERR_UNC_ACSV 0x00200000 /* ACS Violation */
> +#define PCI_ERR_UNC_INTN 0x00400000 /* Internal Error */
> +#define PCI_ERR_UNC_MCBTLP 0x00800000 /* MC Blcoked TLP */
> +#define PCI_ERR_UNC_ATOP_EBLOCKED 0x01000000 /* atomic op egress
> blocked */
> +#define PCI_ERR_UNC_TLP_PRF_BLOCKED 0x02000000 /* TLP Prefix
> Blocked */
> +#define PCI_ERR_COR_ADV_NONFATAL 0x00002000 /* Advisory
> Non-Fatal */
> +#define PCI_ERR_COR_INTERNAL 0x00004000 /* Corrected
> Internal */
> +#define PCI_ERR_COR_HL_OVERFLOW 0x00008000 /* Header Long
> Overflow */
> +#define PCI_ERR_CAP_FEP_MASK 0x0000001f
> +#define PCI_ERR_CAP_MHRC 0x00000200
> +#define PCI_ERR_CAP_MHRE 0x00000400
> +#define PCI_ERR_CAP_TLP 0x00000800
> +
> +#define PCI_ERR_TLP_PREFIX_LOG 0x38
> +
> +#define PCI_SEC_STATUS_RCV_SYSTEM_ERROR 0x4000
> +
> +/* aer root error command/status */
> +#define PCI_ERR_ROOT_CMD_EN_MASK (PCI_ERR_ROOT_CMD_COR_EN | \
> + PCI_ERR_ROOT_CMD_NONFATAL_EN | \
> + PCI_ERR_ROOT_CMD_FATAL_EN)
> +
> +#define PCI_ERR_ROOT_IRQ 0xf8000000
> +#define PCI_ERR_ROOT_IRQ_SHIFT (ffs(PCI_ERR_ROOT_IRQ) - 1)
> +#define PCI_ERR_ROOT_STATUS_REPORT_MASK (PCI_ERR_ROOT_COR_RCV | \
> + PCI_ERR_ROOT_MULTI_COR_RCV | \
> + PCI_ERR_ROOT_UNCOR_RCV | \
> + PCI_ERR_ROOT_MULTI_UNCOR_RCV | \
> + PCI_ERR_ROOT_FIRST_FATAL | \
> + PCI_ERR_ROOT_NONFATAL_RCV | \
> + PCI_ERR_ROOT_FATAL_RCV)
> +
> +#define PCI_ERR_UNC_SUPPORTED (PCI_ERR_UNC_DLP | \
> + PCI_ERR_UNC_SDN | \
> + PCI_ERR_UNC_POISON_TLP | \
> + PCI_ERR_UNC_FCP | \
> + PCI_ERR_UNC_COMP_TIME | \
> + PCI_ERR_UNC_COMP_ABORT | \
> + PCI_ERR_UNC_UNX_COMP | \
> + PCI_ERR_UNC_RX_OVER | \
> + PCI_ERR_UNC_MALF_TLP | \
> + PCI_ERR_UNC_ECRC | \
> + PCI_ERR_UNC_UNSUP | \
> + PCI_ERR_UNC_ACSV | \
> + PCI_ERR_UNC_INTN | \
> + PCI_ERR_UNC_MCBTLP | \
> + PCI_ERR_UNC_ATOP_EBLOCKED | \
> + PCI_ERR_UNC_TLP_PRF_BLOCKED)
> +
> +#define PCI_ERR_UNC_SEVERITY_DEFAULT (PCI_ERR_UNC_DLP | \
> + PCI_ERR_UNC_SDN | \
> + PCI_ERR_UNC_FCP | \
> + PCI_ERR_UNC_RX_OVER | \
> + PCI_ERR_UNC_MALF_TLP | \
> + PCI_ERR_UNC_INTN)
> +
> +#define PCI_ERR_COR_SUPPORTED (PCI_ERR_COR_RCVR | \
> + PCI_ERR_COR_BAD_TLP | \
> + PCI_ERR_COR_BAD_DLLP | \
> + PCI_ERR_COR_REP_ROLL | \
> + PCI_ERR_COR_REP_TIMER | \
> + PCI_ERR_COR_ADV_NONFATAL | \
> + PCI_ERR_COR_INTERNAL | \
> + PCI_ERR_COR_HL_OVERFLOW)
> +
> +#define PCI_ERR_COR_MASK_DEFAULT (PCI_ERR_COR_ADV_NONFATAL | \
> + PCI_ERR_COR_INTERNAL | \
> + PCI_ERR_COR_HL_OVERFLOW)
> +
> +#endif /* QEMU_PCIE_REGS_H */
> --
> 1.7.1.1
