Hi,
Your series seems to have some coding style problems. See output below for
more information:
Type: series
Subject: [Qemu-devel] [PATCH v2 00/16] target-m68k: implement 680x0 FPU
Message-id: 20170130181634.13934-1-laur...@vivier.eu
=== TEST SCRIPT BEGIN ===
#!/bin/bash
BASE=base
n=1
total=$(git log --oneline $BASE.. | wc -l)
failed=0
# Useful git options
git config --local diff.renamelimit 0
git config --local diff.renames True
commits="$(git log --format=%H --reverse $BASE..)"
for c in $commits; do
echo "Checking PATCH $n/$total: $(git log -n 1 --format=%s $c)..."
if ! git show $c --format=email | ./scripts/checkpatch.pl --mailback -; then
failed=1
echo
fi
n=$((n+1))
done
exit $failed
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
* [new tag] patchew/20170130181634.13934-1-laur...@vivier.eu ->
patchew/20170130181634.13934-1-laur...@vivier.eu
Switched to a new branch 'test'
dbe6dbe target-m68k: add fsincos
ab31de0 target-m68k: add more FPU instructions
034d842 target-m68k: add explicit single and double precision operations
6c8776d target-m68k: add fsglmul and fsgldiv
541e299 target-m68k: add fscale, fgetman, fgetexp and fmod
9dfe1c1 target-m68k: add fmovecr
e028b28 target-m68k: add fscc.
aea92d1 target-m68k: add fmovem
5eb013e target-m68k: define 96bit FP registers for gdb on 680x0
9e4f1b4 target-m68k: manage FPU exceptions
baadbd9 target-m68k: add FPCR and FPSR
20f7380 target-m68k: use floatx80 internally
a47c018 target-m68k: define ext_opsize
0770d33 target-m68k: move FPU helpers to fpu_helper.c
4132de8 softloat: disable floatx80_invalid_encoding() for m68k
d714fec softfloat: define 680x0 specific values
=== OUTPUT BEGIN ===
Checking PATCH 1/16: softfloat: define 680x0 specific values...
Checking PATCH 2/16: softloat: disable floatx80_invalid_encoding() for m68k...
Checking PATCH 3/16: target-m68k: move FPU helpers to fpu_helper.c...
Checking PATCH 4/16: target-m68k: define ext_opsize...
Checking PATCH 5/16: target-m68k: use floatx80 internally...
ERROR: storage class should be at the beginning of the declaration
#457: FILE: target/m68k/translate.c:39:
+#define DEFF96(name, offset) static TCGv_i32 QREG_##name##H; \
total: 1 errors, 0 warnings, 1203 lines checked
Your patch has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 6/16: target-m68k: add FPCR and FPSR...
Checking PATCH 7/16: target-m68k: manage FPU exceptions...
Checking PATCH 8/16: target-m68k: define 96bit FP registers for gdb on 680x0...
Checking PATCH 9/16: target-m68k: add fmovem...
Checking PATCH 10/16: target-m68k: add fscc....
Checking PATCH 11/16: target-m68k: add fmovecr...
Checking PATCH 12/16: target-m68k: add fscale, fgetman, fgetexp and fmod...
Checking PATCH 13/16: target-m68k: add fsglmul and fsgldiv...
Checking PATCH 14/16: target-m68k: add explicit single and double precision
operations...
Checking PATCH 15/16: target-m68k: add more FPU instructions...
Checking PATCH 16/16: target-m68k: add fsincos...
=== OUTPUT END ===
Test command exited with code: 1
---
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