Add support for generating the ISS (Instruction Specific Syndrome) for Data Abort exceptions taken from AArch32. These syndromes are used by hypervisors for example to trap and emulate memory accesses.
This is a respin of patch 1/3 from the previous series. Changes v1->v2: * other 2 patches are now in QEMU master * split out the "use pbit/wbit variables" change into its own patch * dropped a few stray blank line changes Otherwise unchanged. thanks -- PMM Peter Maydell (2): target/arm: Abstract out pbit/wbit tests in ARM ldr/str decode target/arm: A32, T32: Create Instruction Syndromes for Data Aborts target/arm/translate.c | 207 ++++++++++++++++++++++++++++++++++++------------- 1 file changed, 155 insertions(+), 52 deletions(-) -- 2.7.4
