On 02/13/2017 01:56 AM, Juro Bystricky wrote: > Add the Altera JTAG UART model. > > Hardware emulation based on: > https://www.altera.com/en_US/pdfs/literature/ug/ug_embedded_ip.pdf > (Please see "Register Map" on page 65) > > Signed-off-by: Juro Bystricky <juro.bystri...@intel.com>
Acked-by: Marek Vasut <ma...@denx.de> -- Best regards, Marek Vasut
