Hi all.
According to "GR712RC Dual-Core LEON3FT SPARC V8 Processor User’s Manual",
"11.3 Registers", pg 87-88, Table 55 Timer control register, the IP
"interrupt pending"
bit:
Interrupt Pending (IP): The core sets this bit to ‘1’ when an interrupt
is signalled. This bit remains ‘1’
until cleared by writing ‘0’ to this bit.
Thus the code handling should changed so that the pending bit is
mantained when "value" has a 1
in that position.
Signed-off-by: Gabriele Galeotti <gabriele.galeotti....@gmail.com>
---
hw/timer/grlib_gptimer.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/hw/timer/grlib_gptimer.c b/hw/timer/grlib_gptimer.c
index 4ed96e9..c555ae8 100644
--- a/hw/timer/grlib_gptimer.c
+++ b/hw/timer/grlib_gptimer.c
@@ -276,9 +276,6 @@ static void grlib_gptimer_write(void *opaque, hwaddr
addr,
trace_grlib_gptimer_writel(id, addr, value);
.
if (value & GPTIMER_INT_PENDING) {
- /* clear pending bit */
- value &= ~GPTIMER_INT_PENDING;
- } else {
/* keep pending bit */
value |= unit->timers[id].config & GPTIMER_INT_PENDING;
}
--.
2.9.0
