[Qemu-devel] [PATCH 13/14] target/sh4: movua.l is an SH4-A only instruction

[Aurelien Jarno]

At the same time change the comment describing the instruction the same
way than other instruction, so that the code is easier to read and search.

Signed-off-by: Aurelien Jarno <aurel...@aurel32.net>
---
 target/sh4/translate.c | 26 +++++++++++++++-----------
 1 file changed, 15 insertions(+), 11 deletions(-)

diff --git a/target/sh4/translate.c b/target/sh4/translate.c
index a158b0e480..bc70166602 100644
--- a/target/sh4/translate.c
+++ b/target/sh4/translate.c
@@ -1502,17 +1502,21 @@ static void _decode_opc(DisasContext * ctx)
         }
         ctx->has_movcal = 1;
        return;
-    case 0x40a9:
-       /* MOVUA.L @Rm,R0 (Rm) -> R0
-          Load non-boundary-aligned data */
-        tcg_gen_qemu_ld_i32(REG(0), REG(B11_8), ctx->memidx, MO_TEUL);
-       return;
-    case 0x40e9:
-       /* MOVUA.L @Rm+,R0   (Rm) -> R0, Rm + 4 -> Rm
-          Load non-boundary-aligned data */
-        tcg_gen_qemu_ld_i32(REG(0), REG(B11_8), ctx->memidx, MO_TEUL);
-       tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4);
-       return;
+    case 0x40a9:                /* movua.l @Rm,R0 */
+        /* Load non-boundary-aligned data */
+        if (ctx->features & SH_FEATURE_SH4A) {
+            tcg_gen_qemu_ld_i32(REG(0), REG(B11_8), ctx->memidx, MO_TEUL);
+            return;
+        }
+        break;
+    case 0x40e9:                /* movua.l @Rm+,R0 */
+        /* Load non-boundary-aligned data */
+        if (ctx->features & SH_FEATURE_SH4A) {
+            tcg_gen_qemu_ld_i32(REG(0), REG(B11_8), ctx->memidx, MO_TEUL);
+            tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4);
+            return;
+        }
+        break;
     case 0x0029:               /* movt Rn */
         tcg_gen_mov_i32(REG(B11_8), cpu_sr_t);
        return;
-- 
2.11.0