On 05/25/2017 02:04 PM, Aurelien Jarno wrote:
Signed-off-by: Aurelien Jarno <aurel...@aurel32.net>
---
target/s390x/insn-data.def | 2 ++
target/s390x/translate.c | 18 ++++++++++++++++++
2 files changed, 20 insertions(+)
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index 53c86d5832..751e3164dd 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -770,6 +770,8 @@
/* STORE ACCESS MULTIPLE */
C(0x9b00, STAM, RS_a, Z, 0, a2, 0, 0, stam, 0)
C(0xeb9b, STAMY, RSY_a, LD, 0, a2, 0, 0, stam, 0)
+/* STORE PAIR TO QUADWORD */
+ C(0xe38e, STPQ, RXY_a, Z, 0, a2, 0, 0, stpq, 0)
Use prep_r1_P here, so that r1 gets validated as even....
+ /* In a parallel context, stop the world and single step. */
+ if (parallel_cpus) {
+ potential_page_fault(s);
+ gen_exception(EXCP_ATOMIC);
+ return EXIT_NORETURN;
+ }
+
+ /* In a serial context, perform the two stores ... */
+ tcg_gen_qemu_st64(regs[r1], o->in2, get_mem_index(s));
+ tcg_gen_addi_i64(o->in2, o->in2, 8);
+ tcg_gen_qemu_st64(regs[r1 + 1], o->in2, get_mem_index(s));
... then use o->out / o->out2 for the stores.
Similarly, helper_atomic_sto_be_mmu in a helper for the parallel context.
r~
