On Fri, Jun 09, 2017 at 10:01:18PM +0200, Gerd Hoffmann wrote: > On Fri, 2017-06-09 at 13:40 +0200, Paolo Bonzini wrote: > > > > On 08/06/2017 21:55, Michael S. Tsirkin wrote: > > > We don't have room anywhere in PCI config space. Laszlo makes > > > argument > > > why it's safe for this device based on spec but it's anyone's guess > > > whether current and future software will follow spec. In short, > > > going > > > anywhere near the emulated device has a potential to break some > > > drivers. > > > > There are no such drivers. The MCH and PCH are only touched by the > > firmware, not by the OS. > > Yea. That is *exactly* the reason why I think simply using the 0x50 > offset probably works fine in practice even though I suspect on > physical hardware it might be some undocumented register. Much of the > stuff in the host bridge pci config space is firmware territory, and we > run qemu specific firmware *anyway*. > > cheers, > Gerd
To be specific, what I meant is a bit that tells guest that a config space register is available, and lets host find out that guest is going to use it. This to ensure full forward and backward compatibility. I agree a fw cfg file for a single bit seems like an overkill, that's why I thought sharing feature files with SMI would be a good idea. Do you see an issue with that? -- MST
