On Fri, Jun 16, 2017 at 11:31:02AM -0500, alar...@ddci.com wrote: > Aaron Larson <alar...@ddci.com> wrote on 06/05/2017 12:22:53 PM: > > > From: Aaron Larson <alar...@ddci.com> > > To: ag...@suse.de, alar...@ddci.com, da...@gibson.dropbear.id.au, > qemu-devel@nongnu.org, qemu-...@nongnu.org > > Date: 06/05/2017 12:22 PM > > Subject: [PATCH v3] target-ppc: Enable open-pic timers to count and > generate interrupts > > > > Previously QEMU open-pic implemented the 4 open-pic timers including > > all timer registers, but the timers did not "count" or generate any > > interrupts. The patch makes the timers both count and generate > > interrupts. The timer clock frequency is fixed at 25MHZ. > > > I haven't received any feedback on this patch, and I don't see a response > on the mailing list archive. Did it get lost?
No, I've just been busy and then sick. I'll get to it eventually..
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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