On 16 June 2017 at 20:41, Alex Bennée <alex.ben...@linaro.org> wrote: > > Peter Maydell <peter.mayd...@linaro.org> writes: > >> Hi; I just noticed that we seem to still implement the ARM v6 >> memory-barrier cp15 ops as NOPs: >> >> { .name = "ISB", .cp = 15, .crn = 7, .crm = 5, .opc1 = 0, .opc2 = 4, >> .access = PL0_W, .type = ARM_CP_NO_RAW, .writefn = arm_cp_write_ignore >> }, >> { .name = "DSB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 4, >> .access = PL0_W, .type = ARM_CP_NOP }, >> { .name = "DMB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 5, >> .access = PL0_W, .type = ARM_CP_NOP }, >> >> Don't these need to do something more complicated with the >> advent of MTTCG ? > > Yeah they should - what does ISB do that it needs a write handler?
The comment just above the ISB definition says: /* We need to break the TB after ISB to execute self-modifying code * correctly and also to take any pending interrupts immediately. * So use arm_cp_write_ignore() function instead of ARM_CP_NOP flag. */ thanks -- PMM