On Fri, Aug 11, 2017 at 12:46 PM, Richard Henderson <richard.hender...@linaro.org> wrote: > On 08/11/2017 11:19 AM, Alistair Francis wrote: >> The exclusive store operation should return 0 if the operation updates >> memory and 1 if it doesn't. This means that storing tmp in the rd >> register is incorrect. > > I'm confused as to what you believe is wrong. > >> tcg_gen_atomic_cmpxchg_i64(tmp, addr, val, tmp, >> get_mem_index(s), >> - size | MO_ALIGN | s->be_data); >> - tcg_gen_setcond_i64(TCG_COND_NE, tmp, tmp, val); > > Yes, we load the result of the cmpxchg into tmp, but then we immediately > overwrite tmp with 0/1 depending on whether the operation succeeded.
Hmmm... When I looked at the values in tmp I was seeing non 0/1 values in there. > >> >> This patch updates the succesful opertion to store 0 into the rd >> register instead of tmp. It also adds a branch to fail if the memory >> isn't updated. > > Since we use setcond, a branch is not required. > >> + tcg_gen_ext_i64(val, val, memop); > > What is this addition intended to accomplish? Because of the position within > the code, you know that memop contains MO_64, so that this is a no-op. This is when size == 2 so it's a 32bit operation so memop contains MO_32. Thanks, Alistair > > > r~