Hi, This series seems to have some coding style problems. See output below for more information:
Type: series Message-id: 20170817180404.29334-1-alex.ben...@linaro.org Subject: [Qemu-devel] [RFC PATCH 0/9] TCG Vector types and example conversion === TEST SCRIPT BEGIN === #!/bin/bash BASE=base n=1 total=$(git log --oneline $BASE.. | wc -l) failed=0 git config --local diff.renamelimit 0 git config --local diff.renames True commits="$(git log --format=%H --reverse $BASE..)" for c in $commits; do echo "Checking PATCH $n/$total: $(git log -n 1 --format=%s $c)..." if ! git show $c --format=email | ./scripts/checkpatch.pl --mailback -; then failed=1 echo fi n=$((n+1)) done exit $failed === TEST SCRIPT END === Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384 Switched to a new branch 'test' bab61192a4 target/arm/translate-a64: vectorise smull vD.4s, vN.[48]s, vM.h[] c5c733a1f9 target/arm/helpers: introduce ADVSIMD flags e27691f07a target/arm/translate-a64: register global vectors 6a55e60454 target/arm/translate-a64: regnames -> x_regnames e7a0e2466b arm/cpu.h: align VFP registers efa94c04ce helper-head: add support for vec type d8c96ebdd2 tcg: generate ptrs to vector registers 26ec07c3d7 tcg: introduce the concepts of a TCGv_vec register type 9ec3b4754d tcg/README: listify the TCG types. === OUTPUT BEGIN === Checking PATCH 1/9: tcg/README: listify the TCG types.... Checking PATCH 2/9: tcg: introduce the concepts of a TCGv_vec register type... Checking PATCH 3/9: tcg: generate ptrs to vector registers... Checking PATCH 4/9: helper-head: add support for vec type... Checking PATCH 5/9: arm/cpu.h: align VFP registers... Checking PATCH 6/9: target/arm/translate-a64: regnames -> x_regnames... Checking PATCH 7/9: target/arm/translate-a64: register global vectors... Checking PATCH 8/9: target/arm/helpers: introduce ADVSIMD flags... WARNING: line over 80 characters #50: FILE: target/arm/advsimd_helper_flags.h:30: + * ADVSIMD_ALL_ELT - the total count of elements (e.g. clear all-opr elements) total: 0 errors, 1 warnings, 65 lines checked Your patch has style problems, please review. If any of these errors are false positives report them to the maintainer, see CHECKPATCH in MAINTAINERS. Checking PATCH 9/9: target/arm/translate-a64: vectorise smull vD.4s, vN.[48]s, vM.h[]... WARNING: line over 80 characters #65: FILE: target/arm/translate-a64.c:10469: +typedef void AdvSIMDGenTwoPlusOneVectorFn(TCGv_vec, TCGv_vec, TCGv_i32, TCGv_i32); ERROR: line over 90 characters #71: FILE: target/arm/translate-a64.c:10475: +static bool handle_vec_simd_mul_addsub(DisasContext *s, uint32_t insn, int opcode, int size, bool is_q, bool u, int rn, int rm, int rd) ERROR: that open brace { should be on the previous line #86: FILE: target/arm/translate-a64.c:10490: + if (!u) + { WARNING: line over 80 characters #95: FILE: target/arm/translate-a64.c:10499: + ADVSIMD_OPR_ELT_SHIFT, ADVSIMD_OPR_ELT_BITS, 4); ERROR: line over 90 characters #99: FILE: target/arm/translate-a64.c:10503: + ADVSIMD_DOFF_ELT_SHIFT, ADVSIMD_DOFF_ELT_BITS, 4); WARNING: line over 80 characters #141: FILE: target/arm/translate-a64.c:10590: + if (handle_vec_simd_mul_addsub(s, insn, opcode, size, is_q, u, rn, rm, rd)) { total: 3 errors, 3 warnings, 109 lines checked Your patch has style problems, please review. If any of these errors are false positives report them to the maintainer, see CHECKPATCH in MAINTAINERS. === OUTPUT END === Test command exited with code: 1 --- Email generated automatically by Patchew [http://patchew.org/]. Please send your feedback to patchew-de...@freelists.org