I see your point. Thank you for the advice. I'm doing some low-level check to be sure to be on a known platform, so this midr based code is very localized. For the "core" of the kernel, I'm mostly using (1) as access to MMU registers are localized in armv7/armv8 specialized sub- directories.
-- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1723984 Title: ID_MMFR0 has an invalid value on aarch64 cpu (A57, A53) Status in QEMU: New Bug description: The ID_MMFR0 register, accessed from aarch64 state as an invalid value: - ARM ARM v8 documentation (D7.2 General system control registers) described bits AuxReg[23:20] to be "In ARMv8-A the only permitted value is 0010" - Cortex A53 and Cortex A57 TRM describe the value to be 0x10201105, so AuxReg[23:20] is 0010 too - in QEMU target/arm/cpu64.c, the relevant value is cpu->id_mmfr0 = 0x10101105; The 1 should be changed to 2. Spotted & Tested on the following qemu revision: commit 48ae1f60d8c9a770e6da64407984d84e25253c69 Merge: 78b62d3 b867eaa Author: Peter Maydell <peter.mayd...@linaro.org> Date: Mon Oct 16 14:28:13 2017 +0100 To manage notifications about this bug go to: https://bugs.launchpad.net/qemu/+bug/1723984/+subscriptions
