On 5 December 2017 at 21:23, Philippe Mathieu-Daudé <f4...@amsat.org> wrote: > The patch is correct, but I don't like having magic values.
Yeah, you're right this would be better. I've already put this patch into target-arm.next, so I'll just squash in this change: --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2258,6 +2258,11 @@ static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx, #define ARM_MMU_IDX_NOTLB 0x20 /* does not have a TLB */ #define ARM_MMU_IDX_M 0x40 /* M profile */ +/* meanings of the bits for M profile mmu idx values */ +#define ARM_MMU_IDX_M_PRIV 0x1 +#define ARM_MMU_IDX_M_NEGPRI 0x2 +#define ARM_MMU_IDX_M_S 0x4 + #define ARM_MMU_IDX_TYPE_MASK (~0x7) #define ARM_MMU_IDX_COREIDX_MASK 0x7 @@ -2328,7 +2333,7 @@ static inline int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx) case ARM_MMU_IDX_A: return mmu_idx & 3; case ARM_MMU_IDX_M: - return mmu_idx & 1; + return mmu_idx & ARM_MMU_IDX_M_PRIV; default: g_assert_not_reached(); } @@ -2342,15 +2347,15 @@ static inline ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, ARMMMUIdx mmu_idx = ARM_MMU_IDX_M; if (el != 0) { - mmu_idx |= 1; + mmu_idx |= ARM_MMU_IDX_M_PRIV; } if (armv7m_nvic_neg_prio_requested(env->nvic, secstate)) { - mmu_idx |= 2; + mmu_idx |= ARM_MMU_IDX_M_NEGPRI; } if (secstate) { - mmu_idx |= 4; + mmu_idx |= ARM_MMU_IDX_M_S; } return mmu_idx; diff --git a/target/arm/helper.c b/target/arm/helper.c index 14ab1f4..70cf313 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7885,10 +7885,7 @@ static inline bool regime_translation_disabled(CPUARMState *env, (R_V7M_MPU_CTRL_ENABLE_MASK | R_V7M_MPU_CTRL_HFNMIENA_MASK)) { case R_V7M_MPU_CTRL_ENABLE_MASK: /* Enabled, but not for HardFault and NMI */ - return mmu_idx == ARMMMUIdx_MUserNegPri || - mmu_idx == ARMMMUIdx_MPrivNegPri || - mmu_idx == ARMMMUIdx_MSUserNegPri || - mmu_idx == ARMMMUIdx_MSPrivNegPri; + return mmu_idx & ARM_MMU_IDX_M_NEGPRI; case R_V7M_MPU_CTRL_ENABLE_MASK | R_V7M_MPU_CTRL_HFNMIENA_MASK: /* Enabled for all cases */ return false; thanks -- PMM