support flr. Signed-off-by: Isaku Yamahata <yamah...@valinux.co.jp> --- hw/pci.c | 6 +++++- hw/pci.h | 1 + hw/pcie.c | 11 +++++------ hw/pcie.h | 2 -- hw/xio3130_downstream.c | 2 +- hw/xio3130_upstream.c | 3 --- 6 files changed, 12 insertions(+), 13 deletions(-)
diff --git a/hw/pci.c b/hw/pci.c index 0cb4117..eb21848 100644 --- a/hw/pci.c +++ b/hw/pci.c @@ -137,7 +137,11 @@ static void pci_update_irq_status(PCIDevice *dev) } } -static void pci_device_reset(PCIDevice *dev) +/* + * This function is called on #RST and FLR. + * FLR if PCI_EXP_DEVCTL_BCR_FLR is set + */ +void pci_device_reset(PCIDevice *dev) { int r; /* TODO: call the below unconditionally once all pci devices diff --git a/hw/pci.h b/hw/pci.h index 17744dc..6e80b08 100644 --- a/hw/pci.h +++ b/hw/pci.h @@ -237,6 +237,7 @@ void pci_bus_hotplug(PCIBus *bus, pci_hotplug_fn hotplug, DeviceState *dev); PCIBus *pci_register_bus(DeviceState *parent, const char *name, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, void *irq_opaque, int devfn_min, int nirq); +void pci_device_reset(PCIDevice *dev); void pci_bus_reset(PCIBus *bus); void pci_bus_set_mem_base(PCIBus *bus, target_phys_addr_t base); diff --git a/hw/pcie.c b/hw/pcie.c index d1f0086..b93fba4 100644 --- a/hw/pcie.c +++ b/hw/pcie.c @@ -380,10 +380,6 @@ void pcie_cap_root_reset(PCIDevice *dev) pci_set_word(dev->config + dev->exp.exp_cap + PCI_EXP_RTCTL, 0); } -/* - * TODO: implement FLR: - * Right now sets the bit which indicates FLR is supported. - */ /* function level reset(FLR) */ void pcie_cap_flr_init(PCIDevice *dev) { @@ -403,8 +399,11 @@ void pcie_cap_flr_write_config(PCIDevice *dev, uint32_t addr, uint32_t val, int len) { uint8_t *devctl = dev->config + dev->exp.exp_cap + PCI_EXP_DEVCTL; - if (pci_word_test_and_clear_mask(devctl, PCI_EXP_DEVCTL_BCR_FLR)) { - /* TODO: implement FLR */ + if (pci_get_word(devctl) & PCI_EXP_DEVCTL_BCR_FLR) { + /* don't clear PCI_EXP_DEVCTL_BCR_FLR to tell reset handler + that this reset is FLR */ + pci_device_reset(dev); + pci_word_test_and_clear_mask(devctl, PCI_EXP_DEVCTL_BCR_FLR); } } diff --git a/hw/pcie.h b/hw/pcie.h index 7baa813..bc909e2 100644 --- a/hw/pcie.h +++ b/hw/pcie.h @@ -63,8 +63,6 @@ struct PCIExpressDevice { /* Offset of express capability in config space */ uint8_t exp_cap; - /* TODO FLR */ - /* SLOT */ unsigned int hpev_intx; /* INTx for hot plug event (0-3:INT[A-D]#) * default is 0 = INTA# diff --git a/hw/xio3130_downstream.c b/hw/xio3130_downstream.c index 1a2d258..5aa6a6b 100644 --- a/hw/xio3130_downstream.c +++ b/hw/xio3130_downstream.c @@ -89,7 +89,7 @@ static int xio3130_downstream_initfn(PCIDevice *d) if (rc < 0) { goto err_msi; } - pcie_cap_flr_init(d); /* TODO: implement FLR */ + pcie_cap_flr_init(d); pcie_cap_deverr_init(d); pcie_cap_slot_init(d, s->slot); pcie_chassis_create(s->chassis); diff --git a/hw/xio3130_upstream.c b/hw/xio3130_upstream.c index 387bf6c..a7640f5 100644 --- a/hw/xio3130_upstream.c +++ b/hw/xio3130_upstream.c @@ -85,10 +85,7 @@ static int xio3130_upstream_initfn(PCIDevice *d) if (rc < 0) { goto err_msi; } - - /* TODO: implement FLR */ pcie_cap_flr_init(d); - pcie_cap_deverr_init(d); rc = pcie_aer_init(d, XIO3130_AER_OFFSET); if (rc < 0) { -- 1.7.1.1