On Tue, Dec 21, 2010 at 02:24:29PM -0600, Adnan Khaleel wrote: > Hello,
Hi. > I have a question regarding how Qemu PCIe devices handle Config Transactions > vs > Memory Transactions (assuming the PCI device is setup to act > as PCI_BASE_ADDRESS_SPACE_MEMORY). > > I'm using portions of hw/cirrus_vga.c to make my point, If you can send out what you have instead of mimicked example, it would help to figure out what you are trying to do. > I have some questions about PCIe operations sssuming the device has MMIO > handlers involved (as shown above). > 1. Will all PCIe config operations ALWAYS use the installed config handlers? > Or > can PCIe config operations use the MMIO handlers? MMIO on MMCONFIG area are routed to write/read config handler. On the other hand MMIO on memory BAR is routed to mmio hanlder you pictured. NOTE: the upstream qemu lacks q35 chipset support, so guest can NOT do MMIO on MMCONFIG area. > 2. Assuming that both PCI config and MMIO operations can use the MMIO > handlers, > is there any way I can identify if a transaction is a config or a memory > transaction? > 3.a. What address is passed on the MMIO handlers for config and MMIO > operations? From pci_data_write in pci_host.c, it appears that config > operations send only the offset into the config region. I couldn't determine > what address is passed for MMIO operations. > b. Is it an offset from the BAR for MMIO operations? > c. How do I get the full physical address? > d. What address does a PCIe device expect to see - physical or offset for? > e. Is there anyway I can find out what the bus and device numbers are once > inside the config and MMIO handlers? i.e once the execution has reached > the pci_cirrus_write_config() or cirrus_vga_mem_readb(..) from the code above? offset in configuration space of each pcie function is passed to write/read config handler physical address is passed to mmio handler of memory BAR. -- yamahata