On Thu, Jan 4, 2018 at 12:23 PM, Eric Blake <ebl...@redhat.com> wrote:
> On 01/02/2018 06:44 PM, Michael Clark wrote:
> > This adds RISC-V into the build system enabling the following targets:
> >
> > - riscv32-softmmu
> > - riscv64-softmmu
> > - riscv32-linux-user
> > - riscv64-linux-user
> >
> > This adds defaults configs for RISC-V, enables the build for the RISC-V
> > CPU core, hardware, and Linux User Emulation. The 'qemu-binfmt-conf.sh'
> > script is updated to add the RISC-V ELF magic.
> >
> > Expected checkpatch errors for consistency reasons:
> >
> > ERROR: line over 90 characters
> > FILE: scripts/qemu-binfmt-conf.sh
> > Signed-off-by: Michael Clark <m...@sifive.com>
> > ---
>
> > +++ b/qapi-schema.json
> > @@ -413,7 +413,7 @@
> > # Since: 2.6
> > ##
> > { 'enum': 'CpuInfoArch',
> > - 'data': ['x86', 'sparc', 'ppc', 'mips', 'tricore', 'other' ] }
> > + 'data': ['x86', 'sparc', 'ppc', 'mips', 'tricore', 'riscv', 'other' ]
> }
>
> Missing documentation that riscv was added in 2.12 (see QKeyCode in
> qapi/ui.json for an enum that serves as an example of documenting
> changes over time).
OK. Will add this in the next spin.
>
> > ##
> > +# @CpuInfoRISCV:
> > +#
> > +# Additional information about a virtual RISCV CPU
> > +#
> > +# @pc: the instruction pointer
> > +#
> > +# Since 2.8
>
> 2.12, actually.
>
> > +##
> > +{ 'struct': 'CpuInfoRISCV', 'data': { 'pc': 'int' } }
>
> Should this be 'uint64' or other specific type, rather than the generic
> 'int' (which happens to be 64 bits, but signed)? Other architectures
> use 'int' because of history, but we could use this chance to improve
> things if desired.
>
I'll have to defer to your better judgement as to whether we need to change
this. I like consistency. Is it a change that needs to be made to multiple
arches? It sounds relatively low risk. You decide.
QAPI Schema
M: Eric Blake <ebl...@redhat.com>
M: Markus Armbruster <arm...@redhat.com>
S: Supported
F: qapi-schema.json
F: qapi/*.json
T: git git://repo.or.cz/qemu/armbru.git qapi-next
