On 18 December 2017 at 17:30, Richard Henderson <[email protected]> wrote: > Enable it for the "any" CPU used by aarch64-linux-user. > > Signed-off-by: Richard Henderson <[email protected]> > --- > target/arm/cpu.h | 1 + > target/arm/cpu64.c | 1 + > 2 files changed, 2 insertions(+) > > diff --git a/target/arm/cpu.h b/target/arm/cpu.h > index 37b8cef2e2..652e00d957 100644 > --- a/target/arm/cpu.h > +++ b/target/arm/cpu.h > @@ -1386,6 +1386,7 @@ enum arm_features { > ARM_FEATURE_V8_1_SIMD, /* has ARMv8.1-SIMD */ > ARM_FEATURE_V8_FP16, /* implements v8.2 half-precision float */ > ARM_FEATURE_V8_FCMA, /* has complex number part of v8.3 extensions. */ > + ARM_FEATURE_SVE, /* has SVE extension */ > }; > > static inline int arm_feature(CPUARMState *env, int feature) > diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c > index 43b42f95fd..366ab2eeee 100644 > --- a/target/arm/cpu64.c > +++ b/target/arm/cpu64.c > @@ -229,6 +229,7 @@ static void aarch64_any_initfn(Object *obj) > set_feature(&cpu->env, ARM_FEATURE_V8_1_SIMD); > set_feature(&cpu->env, ARM_FEATURE_V8_FP16); > set_feature(&cpu->env, ARM_FEATURE_V8_FCMA); > + set_feature(&cpu->env, ARM_FEATURE_SVE); > cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */ > cpu->dcz_blocksize = 7; /* 512 bytes */ > }
We shouldn't turn this on until it actually works, I think. thanks -- PMM
