On 26 January 2018 at 17:33, Wei Xu <xuw...@hisilicon.com> wrote: > On 2018/1/26 17:15, Peter Maydell wrote: >> The pl011 code should call qemu_set_irq(..., 1) when the >> guest enables interrupts on the device by writing to the int_enabled >> (UARTIMSC) register. That will be a 0-to-1 level change and the KVM >> VGIC should report the interrupt to the guest. >> > > Yes. > And in the pl011_update, the irq level is set by s->int_level & > s->int_enabled. > When writing to the int_enabled, not sure why the int_level is set to > 0x20(PL011_INT_TX) but int_enabled is 0x50. > > It still call qemu_set_irq(..., 0). > > I added "s->int_level |= PL011_INT_RX" before calling pl011_update > when writing to the int_enabled and tested it also works.
No, that's not right either. int_level should already have the RX bit set, because pl011_put_fifo() sets that bit when it gets a character from QEMU and puts it into the FIFO. Does something else clear the int_level between the character going into the FIFO from QEMU and the guest enabling interrupts? thanks -- PMM
