On Fri, 23 Feb 2018 13:11:49 +1300 Michael Clark <m...@sifive.com> wrote:
> Add CPU state header, CPU definitions and initialization routines > > Reviewed-by: Richard Henderson <richard.hender...@linaro.org> > Signed-off-by: Michael Clark <m...@sifive.com> > --- > target/riscv/cpu.c | 391 +++++++++++++++++++++++++++++++++++++++++++++ > target/riscv/cpu.h | 256 +++++++++++++++++++++++++++++ > target/riscv/cpu_bits.h | 416 > ++++++++++++++++++++++++++++++++++++++++++++++++ > 3 files changed, 1063 insertions(+) > create mode 100644 target/riscv/cpu.c > create mode 100644 target/riscv/cpu.h > create mode 100644 target/riscv/cpu_bits.h > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c [...] > + > +static const RISCVCPUInfo riscv_cpus[] = { > + { TYPE_RISCV_CPU_ANY, riscv_any_cpu_init }, > + { TYPE_RISCV_CPU_IMAFDCSU_PRIV_1_09, riscv_imafdcsu_priv1_9_cpu_init }, > + { TYPE_RISCV_CPU_IMAFDCSU_PRIV_1_10, riscv_imafdcsu_priv1_10_cpu_init }, > + { TYPE_RISCV_CPU_IMACU_PRIV_1_10, riscv_imacu_priv1_10_cpu_init }, > + { TYPE_RISCV_CPU_IMAC_PRIV_1_10, riscv_imac_priv1_10_cpu_init }, > + { NULL, NULL } > +}; [...] > +static void cpu_register(const RISCVCPUInfo *info) > +{ > + TypeInfo type_info = { > + .name = info->name, > + .parent = TYPE_RISCV_CPU, > + .instance_size = sizeof(RISCVCPU), > + .instance_init = info->initfn, > + }; > + > + type_register(&type_info); > +} [...] > + > +void riscv_cpu_list(FILE *f, fprintf_function cpu_fprintf) > +{ > + const RISCVCPUInfo *info = riscv_cpus; > + > + while (info->name) { > + (*cpu_fprintf)(f, "%s\n", info->name); > + info++; > + } > +} majority targets use object_class_get_list() to get the list of CPU types, you can use cris_cpu_list() as example. > +static void riscv_cpu_register_types(void) > +{ > + const RISCVCPUInfo *info = riscv_cpus; > + > + type_register_static(&riscv_cpu_type_info); > + > + while (info->name) { > + cpu_register(info); > + info++; > + } > +} > + > +type_init(riscv_cpu_register_types) [...] This still hasn't addressed a comment from "[PATCH v4 03/22] RISC-V CPU Core Definition" and uses old approach with RISCVCPUInfo helper structure. Please, use commit 974e58d2 to model after.