On 17 February 2018 at 18:23, Richard Henderson
<richard.hender...@linaro.org> wrote:
> Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
> ---
> target/arm/helper-sve.h | 29 +++++++
> target/arm/sve_helper.c | 211
> +++++++++++++++++++++++++++++++++++++++++++++
> target/arm/translate-sve.c | 68 ++++++++++++++-
> target/arm/sve.decode | 38 ++++++++
> 4 files changed, 343 insertions(+), 3 deletions(-)
> diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
> index aa8bfd2ae7..fda9a56fd5 100644
> --- a/target/arm/translate-sve.c
> +++ b/target/arm/translate-sve.c
> @@ -3320,7 +3320,6 @@ static void do_mem_zpa(DisasContext *s, int zt, int pg,
> TCGv_i64 addr,
>
> tcg_temp_free_ptr(t_pg);
> tcg_temp_free_i32(desc);
> - tcg_temp_free_i64(addr);
> }
>
> static void do_ld_zpa(DisasContext *s, int zt, int pg,
> @@ -3368,7 +3367,7 @@ static void trans_LD_zprr(DisasContext *s,
> arg_rprr_load *a, uint32_t insn)
> return;
> }
>
> - addr = tcg_temp_new_i64();
> + addr = new_tmp_a64(s);
> tcg_gen_muli_i64(addr, cpu_reg(s, a->rm),
> (a->nreg + 1) << dtype_msz(a->dtype));
> tcg_gen_add_i64(addr, addr, cpu_reg_sp(s, a->rn));
> @@ -3379,7 +3378,7 @@ static void trans_LD_zpri(DisasContext *s,
> arg_rpri_load *a, uint32_t insn)
> {
> unsigned vsz = vec_full_reg_size(s);
> unsigned elements = vsz >> dtype_esz[a->dtype];
> - TCGv_i64 addr = tcg_temp_new_i64();
> + TCGv_i64 addr = new_tmp_a64(s);
>
> tcg_gen_addi_i64(addr, cpu_reg_sp(s, a->rn),
> (a->imm * elements * (a->nreg + 1))
These changes to the load functions look like they should have been
in the previous patch ?
Otherwise
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
thanks
-- PMM
