On 28 February 2018 at 19:31, Richard Henderson <richard.hender...@linaro.org> wrote: > Enable it for the "any" CPU used by *-linux-user. > > Signed-off-by: Richard Henderson <richard.hender...@linaro.org> > --- > target/arm/cpu.c | 1 + > target/arm/cpu64.c | 1 + > 2 files changed, 2 insertions(+) > > diff --git a/target/arm/cpu.c b/target/arm/cpu.c > index ca5fb1162a..452bc32f10 100644 > --- a/target/arm/cpu.c > +++ b/target/arm/cpu.c > @@ -1651,6 +1651,7 @@ static void arm_any_initfn(Object *obj) > set_feature(&cpu->env, ARM_FEATURE_V8_PMULL); > set_feature(&cpu->env, ARM_FEATURE_CRC); > set_feature(&cpu->env, ARM_FEATURE_V8_RDM); > + set_feature(&cpu->env, ARM_FEATURE_V8_FCMA); > cpu->midr = 0xffffffff; > } > #endif > diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c > index 7246866e7d..4228713b19 100644 > --- a/target/arm/cpu64.c > +++ b/target/arm/cpu64.c > @@ -232,6 +232,7 @@ static void aarch64_any_initfn(Object *obj) > set_feature(&cpu->env, ARM_FEATURE_CRC); > set_feature(&cpu->env, ARM_FEATURE_V8_RDM); > set_feature(&cpu->env, ARM_FEATURE_V8_FP16); > + set_feature(&cpu->env, ARM_FEATURE_V8_FCMA); > cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */ > cpu->dcz_blocksize = 7; /* 512 bytes */ > } > --
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org> We should be setting some hwcap bits in linux-user for these new feature bits (and RDM), right? thanks -- PMM
