For the Arm target, we have a 3-operand tcg_insn_start, where the 3 arguments are the PC, condexec bits, and a syndrome value. We set it up like this:
tcg_gen_insn_start(dc->pc, (dc->condexec_cond << 4) | (dc->condexec_mask >> 1), 0); dc->insn_start = tcg_last_op(); and then we patch in the 3rd operand later in disas_set_insn_syndrome(): tcg_set_insn_param(s->insn_start, 2, syn); Unfortunately, if we're running on a setup where TARGET_LONG_BITS > TCG_TARGET_REG_BITS (ie 64 bit guest on 32 bit host), tcg_gen_insn_start() has under the hood split the 3 operands we gave it into 6, and so we end up patching a syndrome value into the condexec bits. This means we'll end up with corrupted guest condexec state if we have to do a cpu_restore_state(), which happens often when using icount and occasionally for load/store instructions that fault. Fix the bug by using the correct operand offset for the 64-on-32 case. Cc: qemu-sta...@nongnu.org Reported-by: alar...@ddci.com Signed-off-by: Peter Maydell <peter.mayd...@linaro.org> --- This doesn't apply as-is to the stable branch, but the difference is minor (insn_start was insn_start_idx, but the 2 vs 4 for argument 2 is still the same.) --- target/arm/translate.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/target/arm/translate.h b/target/arm/translate.h index c47febf99d..f04ece9cfd 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -120,7 +120,15 @@ static inline void disas_set_insn_syndrome(DisasContext *s, uint32_t syn) /* We check and clear insn_start_idx to catch multiple updates. */ assert(s->insn_start != NULL); +#if TARGET_LONG_BITS <= TCG_TARGET_REG_BITS tcg_set_insn_param(s->insn_start, 2, syn); +#else + /* tcg_gen_insn_start has split every target_ulong argument to + * op_insn_start into two 32-bit arguments, so we want the low + * half of the 3rd argument, which is at index 4. + */ + tcg_set_insn_param(s->insn_start, 4, syn); +#endif s->insn_start = NULL; } -- 2.16.2