From: Onur Sahin <onursahi...@gmail.com>
Make sure we are not treating architecturally Undefined instructions
as a SWP, by verifying the opcodes as per section A8.8.229 of ARMv7-A
specification. Bits [21:20] must be zero for this to be a SWP or SWPB.
We also choose to UNDEF for the architecturally UNPREDICTABLE case of
bits [11:8] not being zero.
Signed-off-by: Onur Sahin <onursahi...@gmail.com>
[PMM: tweaked commit message]
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
---
target/arm/translate.c | 9 +++++++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index fc03b5b8c8..db1ce6510a 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -9237,11 +9237,14 @@ static void disas_arm_insn(DisasContext *s, unsigned
int insn)
}
}
tcg_temp_free_i32(addr);
- } else {
+ } else if ((insn & 0x00300f00) == 0) {
+ /* 0bcccc_0001_0x00_xxxx_xxxx_0000_1001_xxxx
+ * - SWP, SWPB
+ */
+
TCGv taddr;
TCGMemOp opc = s->be_data;
- /* SWP instruction */
rm = (insn) & 0xf;
if (insn & (1 << 22)) {
@@ -9259,6 +9262,8 @@ static void disas_arm_insn(DisasContext *s, unsigned int
insn)
get_mem_index(s), opc);
tcg_temp_free(taddr);
store_reg(s, rd, tmp);
+ } else {
+ goto illegal_op;
}
}
} else {
--
2.16.2
