On Apr 12 13:36, Aaron Lindsay wrote: > On Apr 12 18:15, Peter Maydell wrote: > > On 16 March 2018 at 20:31, Aaron Lindsay <alind...@codeaurora.org> wrote: > > > diff --git a/target/arm/cpu.h b/target/arm/cpu.h > > > index b0ef727..9c3b5ef 100644 > > > --- a/target/arm/cpu.h > > > +++ b/target/arm/cpu.h > > > @@ -458,6 +458,11 @@ typedef struct CPUARMState { > > > * was reset. Otherwise it stores the counter value > > > */ > > > uint64_t c15_ccnt; > > > + /* ccnt_cached_cycles is used to hold the last cycle count when > > > + * c15_ccnt holds the guest-visible count instead of the delta > > > during > > > + * PMU operations which require this. > > > + */ > > > + uint64_t ccnt_cached_cycles; > > > > Can this ever hold valid state at a point when we need to do VM > > migration, or is it purely temporary ? > > I believe that as of this version of the patch it is temporary and will > not need to be migrated. However, I believe it's going to be necessary > to have two variables to represent the state of each counter in order to > implement interrupt on overflow.
Coming back around to this, I don't see a way around using two variables to hold PMCCNTR's full state to make interrupt on overflow work. I haven't been able to find other examples or documentation covering state needing to be updated in more than one location for a given CP register - do you know of any I've missed or have recommendations about how to approach this? -Aaron -- Qualcomm Datacenter Technologies as an affiliate of Qualcomm Technologies, Inc. Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project.