From: "Edgar E. Iglesias" <edgar.igles...@xilinx.com>
Fix trap checks for FPU insns when extended FPU insns are enabled.
Reviewed-by: Alistair Francis <alistair.fran...@wdc.com>
Signed-off-by: Edgar E. Iglesias <edgar.igles...@xilinx.com>
---
target/microblaze/translate.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
index f739751930..ec12fed49d 100644
--- a/target/microblaze/translate.c
+++ b/target/microblaze/translate.c
@@ -1412,7 +1412,7 @@ static void dec_fpu(DisasContext *dc)
if ((dc->tb_flags & MSR_EE_FLAG)
&& (dc->cpu->env.pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
- && (dc->cpu->cfg.use_fpu != 1)) {
+ && !dc->cpu->cfg.use_fpu) {
tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
t_gen_raise_exception(dc, EXCP_HW_EXCP);
return;
--
2.14.1
