Alex Bennée <alex.ben...@linaro.org> writes: > Richard Henderson <richard.hender...@linaro.org> writes: > >> When running the gcc testsuite with current aarch64-linux-user, >> the testsuite detects the presence of the fp16 extension and >> enables lots of extra tests for builtins. >> >> Quite a few of these new tests fail because we missed implementing >> some instructions. We really should go back and verify that nothing >> else is missing from this (rather large) extension. > > So this set of instructions is generated from any ASL description that > contains "half": <snip> > > Failed 9 tests: > testcases.armv8.2_half/insn_FCCMP_H_floatccmp__INC.risu.bin > testcases.armv8.2_half/insn_FCCMPE_H_floatccmp__INC.risu.bin > testcases.armv8.2_half/insn_FCMP_H_floatcmp__INC.risu.bin > testcases.armv8.2_half/insn_FCMP_HZ_floatcmp__INC.risu.bin > testcases.armv8.2_half/insn_FCMPE_H_floatcmp__INC.risu.bin > testcases.armv8.2_half/insn_FCMPE_HZ_floatcmp__INC.risu.bin > testcases.armv8.2_half/insn_FCSEL_H_floatsel__INC.risu.bin
Well that looks like a whole class of compares we are missing. I'll get to work on that. > testcases.armv8.2_half/insn_FMOV_H_floatimm__INC.risu.bin > testcases.armv8.2_half/insn_FSQRT_H_floatdp1__INC.risu.bin > > but I haven't checked to see if that is just instructions the FVP has in > full SVE mode that aren't in the just FP16 fixes branch I was testing > against. > > >> >> In addition, it tests some edge conditions on data that show flaws >> in the way we were performing integer<->fp conversion; particularly >> with respect to scaled conversion. >> >> >> r~ >> >> PS: FWIW, this was written against my tgt-arm-sve-9 tree, since I >> was trying to test sve as generated by gcc. I don't *think* there >> are any dependencies on any of the sve patches, but I didn't check. >> >> PPS: There are two more failures that might be qemu fp16 failures, >> but those are SIGSEGV. This patch set cures all of the SIGILL and >> (subsequent) SIGABRT type failures within the testsuite. >> >> >> Richard Henderson (9): >> target/arm: Implement vector shifted SCVF/UCVF for fp16 >> target/arm: Implement vector shifted FCVT for fp16 >> target/arm: Fix float16 to/from int16 >> target/arm: Clear SVE high bits for FMOV >> target/arm: Implement FMOV (general) for fp16 >> target/arm: Implement FCVT (scalar,integer) for fp16 >> target/arm: Implement FCVT (scalar,fixed-point) for fp16 >> target/arm: Implement FP data-processing (2 source) for fp16 >> target/arm: Implement FP data-processing (3 source) for fp16 >> >> target/arm/helper.h | 6 + >> target/arm/helper.c | 87 ++++++++++- >> target/arm/translate-a64.c | 371 >> +++++++++++++++++++++++++++++++++++++-------- >> 3 files changed, 399 insertions(+), 65 deletions(-) -- Alex Bennée