On 6 May 2018 at 00:35, Michael Clark <m...@sifive.com> wrote: > The following changes since commit c8b7e627b4269a3bc3ae41d9f420547a47e6d9b9: > > Merge remote-tracking branch 'remotes/ericb/tags/pull-nbd-2018-05-04' into > staging (2018-05-04 14:42:46 +0100) > > are available in the git repository at: > > https://github.com/riscv/riscv-qemu.git tags/riscv-qemu-2.13-pull-20180506 > > for you to fetch changes up to 5aec3247c190f10654250203a1742490ae7343a2: > > RISC-V: Mark ROM read-only after copying in code (2018-05-06 10:54:21 +1200) > > ---------------------------------------------------------------- > RISC-V: QEMU 2.13 Privileged ISA emulation updates > > Several code cleanups, minor specification conformance changes, > fixes to make ROM read-only and add device-tree size checks. > > * Honour privileged ISA v1.10 counter enable CSRs. > * Implements WARL behavior for CSRs that don't support writes > * Past behavior of raising traps was non-conformant > with the RISC-V Privileged ISA Specification v1.10. > * Allow S-mode access to sstatus.MXR when priv ISA >= v1.10 > * Sets mtval/stval to zero on exceptions without addresses > * Past behavior of leaving the last value was non-conformant > with the RISC-V Privileged ISA Specition v1.10. mtval/stval > must be set on all exceptions; to zero if not supported. > * Make ROMs read-only and implement device-tree size checks > * Uses memory_region_init_rom and rom_add_blob_fixed_as > * Adds hexidecimal instruction bytes to disassembly output. > * Fixes missing break statement for rv128 disassembly. > * Several code cleanups > * Replacing hard-coded constants with enums > * Dead-code elimination > > This is an incremental pull that contains 20 reviewed changes out > of 38 changes currently queued in the qemu-2.13-for-upstream branch. >
Applied, thanks. -- PMM