On 14 May 2018 at 23:12, Richard Henderson <richard.hender...@linaro.org> wrote:
> From: Alex Bennée <alex.ben...@linaro.org>
>
> Instead of passing env and leaving it up to the helper to get the
> right fpstatus we pass it explicitly. There was already a get_fpstatus
> helper for neon for the 32 bit code. We also add an get_ahp_flag() for
> passing the state of the alternative FP16 format flag. This leaves
> scope for later tracking the AHP state in translation flags.
>
> Signed-off-by: Alex Bennée <alex.ben...@linaro.org>
> Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
>
> ---
> v4
> - remove neon_fcvt_*; they are now identical to vfp_fcvt_*.
> - add flags to vfp_fcvt_* helper decls.
> - add some missing tcg_temp_free_*.
> v5
> - always use get_fpstatus_ptr(false) for FZ, since FZ16 is
> supposed to be supressed.
> ---
> @@ -9053,12 +9066,17 @@ static void handle_2misc_narrow(DisasContext *s, bool
> scalar,
> } else {
> TCGv_i32 tcg_lo = tcg_temp_new_i32();
> TCGv_i32 tcg_hi = tcg_temp_new_i32();
> + TCGv_ptr fpst = get_fpstatus_ptr(true);
Still the wrong fpstatus here...
> + TCGv_i32 ahp = get_ahp_flag();
> +
> tcg_gen_extr_i64_i32(tcg_lo, tcg_hi, tcg_op);
> - gen_helper_vfp_fcvt_f32_to_f16(tcg_lo, tcg_lo, cpu_env);
> - gen_helper_vfp_fcvt_f32_to_f16(tcg_hi, tcg_hi, cpu_env);
> + gen_helper_vfp_fcvt_f32_to_f16(tcg_lo, tcg_lo, fpst, ahp);
> + gen_helper_vfp_fcvt_f32_to_f16(tcg_hi, tcg_hi, fpst, ahp);
> tcg_gen_deposit_i32(tcg_res[pass], tcg_lo, tcg_hi, 16, 16);
> tcg_temp_free_i32(tcg_lo);
> tcg_temp_free_i32(tcg_hi);
> + tcg_temp_free_ptr(fpst);
> + tcg_temp_free_i32(ahp);
> }
> break;
> case 0x56: /* FCVTXN, FCVTXN2 */
> @@ -11532,18 +11550,24 @@ static void handle_2misc_widening(DisasContext *s,
> int opcode, bool is_q,
> /* 16 -> 32 bit fp conversion */
> int srcelt = is_q ? 4 : 0;
> TCGv_i32 tcg_res[4];
> + TCGv_ptr fpst = get_fpstatus_ptr(true);
...and here.
> + TCGv_i32 ahp = get_ahp_flag();
> +
>
> for (pass = 0; pass < 4; pass++) {
> tcg_res[pass] = tcg_temp_new_i32();
>
> read_vec_element_i32(s, tcg_res[pass], rn, srcelt + pass, MO_16);
> gen_helper_vfp_fcvt_f16_to_f32(tcg_res[pass], tcg_res[pass],
> - cpu_env);
> + fpst, ahp);
> }
> for (pass = 0; pass < 4; pass++) {
> write_vec_element_i32(s, tcg_res[pass], rd, pass, MO_32);
> tcg_temp_free_i32(tcg_res[pass]);
> }
> +
> + tcg_temp_free_ptr(fpst);
> + tcg_temp_free_i32(ahp);
> }
> }
thanks
-- PMM
