On 01.02.2011, at 18:06, Aurelien Jarno wrote: > On Tue, Feb 01, 2011 at 05:53:43PM +0100, Alexander Graf wrote: >> >> On 01.02.2011, at 17:34, Aurelien Jarno wrote: >> >>> On Tue, Feb 01, 2011 at 03:51:32PM +0100, Alexander Graf wrote: >>>> When using level based interrupts, the interrupt is treated the same as an >>>> edge triggered one: leaving the line up does not retrigger the interrupt. >>>> >>>> In fact, when not lowering the line, we won't ever get a new interrupt >>>> inside >>>> the guest. So let's always retrigger an interrupt as soon as the OS ack'ed >>>> something on the device. This way we're sure the guest doesn't starve on >>>> interrupts until someone fixes the actual interrupt path. >>> >>> Given this issue mostly concerns x86 and not other architectures where >>> the SATA emulation can probably be used, what about putting the two >>> versions of the codes like in i8259.c: >>> >>> | * all targets should do this rather than acking the IRQ in the cpu */ >>> | #if defined(TARGET_MIPS) || defined(TARGET_PPC) || defined(TARGET_ALPHA) >>> >>> The list of architectures here is reduced given the few architectures >>> that actually use the i8259, so for ahci.c it should probably be #if not >>> defined(TARGET_I386) instead. >> >> Because then we'd have to build the ahci code conditionally on the >> architecture. Right now it builds into libhw :) > > If we want to keep it in libhw, it's probably better to disable it on > other architectures than i386.
How so? The workaround simply triggers a superfluous interrupt event, but shouldn't break anything for other architectures. In fact, last time I checked it worked just fine on ppc. Alex