The primary aim of this patch series is to fix the decoding of the preload and hint instruction space (PLD, PLDW, PLI). Some of these instructions (PLDW and some unallocated space which should NOP) are v7MP only, so we introduce a feature flag for cores with the v7MP extensions.
The flag also lets us clean up the MPIDR coprocessor register implementation so it isn't A9 specific any more. Tested as usual with random instruction sequences. Peter Maydell (4): target-arm: Add CPU feature flag for v7MP target-arm: Clean up handling of MPIDR target-arm: Fix decoding of preload and memory hint space target-arm: Fix decoding of Thumb preload and hint space target-arm/cpu.h | 3 +- target-arm/helper.c | 32 +++++++++++++-- target-arm/translate.c | 98 +++++++++++++++++++++++++++++++++++------------ 3 files changed, 102 insertions(+), 31 deletions(-)
