On Fri, Jun 15, 2018 at 05:25:34PM +0200, Cédric Le Goater wrote: > This moves the details of the ISA bus creation under the LPC model but > more important, the new PnvChip operation will let us choose the chip > class to use when we introduce the different chip classes for Power9 > and Power8. It hides away the processor chip controllers from the > machine. > > Signed-off-by: Cédric Le Goater <c...@kaod.org>
Applied to ppc-for-3.0, thanks.
> ---
>
> pnv_isa_create() is a onliner but it looks better like that than to
> use it directly with pnv->chips[0]
>
> include/hw/ppc/pnv.h | 1 +
> include/hw/ppc/pnv_lpc.h | 3 +--
> hw/ppc/pnv.c | 34 +++++++++++++++++++---------------
> hw/ppc/pnv_lpc.c | 30 +++++++++++++++++++++++++-----
> 4 files changed, 46 insertions(+), 22 deletions(-)
>
> diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h
> index e934e84f555e..563279f3e00c 100644
> --- a/include/hw/ppc/pnv.h
> +++ b/include/hw/ppc/pnv.h
> @@ -77,6 +77,7 @@ typedef struct PnvChipClass {
>
> uint32_t (*core_pir)(PnvChip *chip, uint32_t core_id);
> Object *(*intc_create)(PnvChip *chip, Object *child, Error **errp);
> + ISABus *(*isa_create)(PnvChip *chip, Error **errp);
> } PnvChipClass;
>
> #define PNV_CHIP_TYPE_SUFFIX "-" TYPE_PNV_CHIP
> diff --git a/include/hw/ppc/pnv_lpc.h b/include/hw/ppc/pnv_lpc.h
> index 53fdd5bb6450..d657489b07ce 100644
> --- a/include/hw/ppc/pnv_lpc.h
> +++ b/include/hw/ppc/pnv_lpc.h
> @@ -70,7 +70,6 @@ typedef struct PnvLpcController {
> PnvPsi *psi;
> } PnvLpcController;
>
> -qemu_irq *pnv_lpc_isa_irq_create(PnvLpcController *lpc, int chip_type,
> - int nirqs);
> +ISABus *pnv_lpc_isa_create(PnvLpcController *lpc, bool use_cpld, Error
> **errp);
>
> #endif /* _PPC_PNV_LPC_H */
> diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
> index c7e127ae97db..ac828d133173 100644
> --- a/hw/ppc/pnv.c
> +++ b/hw/ppc/pnv.c
> @@ -529,24 +529,24 @@ static void pnv_reset(void)
> cpu_physical_memory_write(PNV_FDT_ADDR, fdt, fdt_totalsize(fdt));
> }
>
> -static ISABus *pnv_isa_create(PnvChip *chip)
> +static ISABus *pnv_chip_power8_isa_create(PnvChip *chip, Error **errp)
> {
> - PnvLpcController *lpc = &chip->lpc;
> - ISABus *isa_bus;
> - qemu_irq *irqs;
> - PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
> + return pnv_lpc_isa_create(&chip->lpc, true, errp);
> +}
>
> - /* let isa_bus_new() create its own bridge on SysBus otherwise
> - * devices speficied on the command line won't find the bus and
> - * will fail to create.
> - */
> - isa_bus = isa_bus_new(NULL, &lpc->isa_mem, &lpc->isa_io,
> - &error_fatal);
> +static ISABus *pnv_chip_power8nvl_isa_create(PnvChip *chip, Error **errp)
> +{
> + return pnv_lpc_isa_create(&chip->lpc, false, errp);
> +}
>
> - irqs = pnv_lpc_isa_irq_create(lpc, pcc->chip_type, ISA_NUM_IRQS);
> +static ISABus *pnv_chip_power9_isa_create(PnvChip *chip, Error **errp)
> +{
> + return NULL;
> +}
>
> - isa_bus_irqs(isa_bus, irqs);
> - return isa_bus;
> +static ISABus *pnv_isa_create(PnvChip *chip, Error **errp)
> +{
> + return PNV_CHIP_GET_CLASS(chip)->isa_create(chip, errp);
> }
>
> static void pnv_init(MachineState *machine)
> @@ -646,7 +646,7 @@ static void pnv_init(MachineState *machine)
> g_free(chip_typename);
>
> /* Instantiate ISA bus on chip 0 */
> - pnv->isa_bus = pnv_isa_create(pnv->chips[0]);
> + pnv->isa_bus = pnv_isa_create(pnv->chips[0], &error_fatal);
>
> /* Create serial port */
> serial_hds_isa_init(pnv->isa_bus, 0, MAX_ISA_SERIAL_PORTS);
> @@ -735,6 +735,7 @@ static void pnv_chip_power8e_class_init(ObjectClass
> *klass, void *data)
> k->cores_mask = POWER8E_CORE_MASK;
> k->core_pir = pnv_chip_core_pir_p8;
> k->intc_create = pnv_chip_power8_intc_create;
> + k->isa_create = pnv_chip_power8_isa_create;
> k->xscom_base = 0x003fc0000000000ull;
> dc->desc = "PowerNV Chip POWER8E";
> }
> @@ -749,6 +750,7 @@ static void pnv_chip_power8_class_init(ObjectClass
> *klass, void *data)
> k->cores_mask = POWER8_CORE_MASK;
> k->core_pir = pnv_chip_core_pir_p8;
> k->intc_create = pnv_chip_power8_intc_create;
> + k->isa_create = pnv_chip_power8_isa_create;
> k->xscom_base = 0x003fc0000000000ull;
> dc->desc = "PowerNV Chip POWER8";
> }
> @@ -763,6 +765,7 @@ static void pnv_chip_power8nvl_class_init(ObjectClass
> *klass, void *data)
> k->cores_mask = POWER8_CORE_MASK;
> k->core_pir = pnv_chip_core_pir_p8;
> k->intc_create = pnv_chip_power8_intc_create;
> + k->isa_create = pnv_chip_power8nvl_isa_create;
> k->xscom_base = 0x003fc0000000000ull;
> dc->desc = "PowerNV Chip POWER8NVL";
> }
> @@ -777,6 +780,7 @@ static void pnv_chip_power9_class_init(ObjectClass
> *klass, void *data)
> k->cores_mask = POWER9_CORE_MASK;
> k->core_pir = pnv_chip_core_pir_p9;
> k->intc_create = pnv_chip_power9_intc_create;
> + k->isa_create = pnv_chip_power9_isa_create;
> k->xscom_base = 0x00603fc00000000ull;
> dc->desc = "PowerNV Chip POWER9";
> }
> diff --git a/hw/ppc/pnv_lpc.c b/hw/ppc/pnv_lpc.c
> index 402c4fefa886..d7721320a25b 100644
> --- a/hw/ppc/pnv_lpc.c
> +++ b/hw/ppc/pnv_lpc.c
> @@ -22,6 +22,7 @@
> #include "target/ppc/cpu.h"
> #include "qapi/error.h"
> #include "qemu/log.h"
> +#include "hw/isa/isa.h"
>
> #include "hw/ppc/pnv.h"
> #include "hw/ppc/pnv_lpc.h"
> @@ -535,16 +536,35 @@ static void pnv_lpc_isa_irq_handler(void *opaque, int
> n, int level)
> }
> }
>
> -qemu_irq *pnv_lpc_isa_irq_create(PnvLpcController *lpc, int chip_type,
> - int nirqs)
> +ISABus *pnv_lpc_isa_create(PnvLpcController *lpc, bool use_cpld, Error
> **errp)
> {
> + Error *local_err = NULL;
> + ISABus *isa_bus;
> + qemu_irq *irqs;
> + qemu_irq_handler handler;
> +
> + /* let isa_bus_new() create its own bridge on SysBus otherwise
> + * devices speficied on the command line won't find the bus and
> + * will fail to create.
> + */
> + isa_bus = isa_bus_new(NULL, &lpc->isa_mem, &lpc->isa_io, &local_err);
> + if (local_err) {
> + error_propagate(errp, local_err);
> + return NULL;
> + }
> +
> /* Not all variants have a working serial irq decoder. If not,
> * handling of LPC interrupts becomes a platform issue (some
> * platforms have a CPLD to do it).
> */
> - if (chip_type == PNV_CHIP_POWER8NVL) {
> - return qemu_allocate_irqs(pnv_lpc_isa_irq_handler, lpc, nirqs);
> + if (use_cpld) {
> + handler = pnv_lpc_isa_irq_handler_cpld;
> } else {
> - return qemu_allocate_irqs(pnv_lpc_isa_irq_handler_cpld, lpc, nirqs);
> + handler = pnv_lpc_isa_irq_handler;
> }
> +
> + irqs = qemu_allocate_irqs(handler, lpc, ISA_NUM_IRQS);
> +
> + isa_bus_irqs(isa_bus, irqs);
> + return isa_bus;
> }
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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