On 19 June 2018 at 21:42, Julia Suvorova <jus...@mail.ru> wrote: > Unlike ARMv7-M, ARMv6-M only supports naturally aligned memory accesses > for 16-bit halfword and 32-bit word accesses using the LDR, LDRH, > LDRSH, STR and STRH instructions. > > Signed-off-by: Julia Suvorova <jus...@mail.ru> > --- > target/arm/translate.c | 18 ++++++++++++++++-- > 1 file changed, 16 insertions(+), 2 deletions(-) > > diff --git a/target/arm/translate.c b/target/arm/translate.c > index b988d379e7..d923cbe98e 100644 > --- a/target/arm/translate.c > +++ b/target/arm/translate.c > @@ -1100,7 +1100,14 @@ static inline TCGv gen_aa32_addr(DisasContext *s, > TCGv_i32 a32, TCGMemOp op) > static void gen_aa32_ld_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32, > int index, TCGMemOp opc) > { > - TCGv addr = gen_aa32_addr(s, a32, opc); > + TCGv addr; > + > + if (arm_dc_feature(s, ARM_FEATURE_M) && > + !arm_dc_feature(s, ARM_FEATURE_V7)) { > + opc |= MO_ALIGN; > + }
Hi; I think this is a good point to introduce a ARM_FEATURE_M_MAIN feature bit, because this is one of those places where v8M baseline and v6M are the same. Basically: * add a line to the enum arm_features: ARM_FEATURE_M_MAIN, /* M profile Main Extension */ * add set_feature() calls to cortex_m3/m4/m33_initfn() which set that feature * don't set the feature for the cortex-m0 * in these checks, use if (arm_dc_feature(s, ARM_FEATURE_M) && !arm_dc_feature(s, ARM_FEATURE_M_MAIN)) { A lot of the v6M checks are going to also apply for v8M baseline, so it'll be time saved later to use the feature bit. (Alignment checks are a bit more complicated as strictly v7M has a config register bit to allow turning them on, but let's not worry about that. We can refactor the code later if we ever care about implementing that.) thanks -- PMM